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  1. Intel MAX 10 10M08 FPGA SoC, U1
  2. 8 Mbyte SDRAM 166MHz, U2
  3. 8 Mbyte SPI QSPI Flash memory, U5
  4. ST Microelectronics LIS3DH 3-axis accelerometer, U4
  5. FTDI USB2 to JTAG/UART adapter, U3
  6. Configuration EEPROM for FTDI chip, U9
  7. 12.0000 MHz oscillator, U7
  8. 8x red user LEDs, D2 ... D9
  9. Red LED (Conf. DONE), D10
  10. Green LED (indicating supply voltage), D1
  11. Push button (user), S2
  12. Push button (reset), S1
  13. Micro USB2 B socket (receptacle), J9
  14. 1x14 pin header (2.54mm pitch), J2
  15. 1x6 pin header (2.54mm pitch), J4
  16. 2x6 Pmod connector, J6
  17. 3-pin header (2.54mm pitch), J3
  18. 1x14 pin header (2.54mm pitch), J1

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Storage device name

Content

Notes

Quad SPI Flash, U5

DEMO Design

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I2C Configuration EEPROM, U9

Programmed

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BankI/O's CountConnected toNotes
241x14 pin header, J1user GPIO's
8Pmod connector, J6user GPIO's
1clock oscillator, U712.0000 MHz reference clock input
1optional clock oscillator, U6oscillator not fitted, footprints available for Microchip MEMS oscillator
591x14 pin header, J22 I/O's (D11, D12) of bank 5 can be pulled-up to 3.3V (4K7 resistors) with 1 I/O (D12_R) of same Bank and 1 I/O (D11_R) of bank 6
6188 MByte SDRAM 166MHz, U216bit SDRAM memory interface
3228 MByte SDRAM 166MHz, U216bit SDRAM memory interface
6LIS3DH 3-axis accelerometer, U44 I/O's for SPI interface, 2 interrupt lines
1A81x14 pin headers J17 analog inputs or GPIO's, 1 pin analog reference voltage input
2pin headers J11 analog inputs or GPIO, 1 dedicated analog input
1B5pin header J44 I/O's JTAG interface and 1x 'JTAGEN' signal to switch the JTAG pins to user GPIO's if drive this pin to GND
88LEDs D2 ... D9Red user LEDs
6SPI Flash memory, U54 6 pins Quad SPI interface, 2 control linesof them pulled up as configuration pins during initialization
6FTDI FT2232H JTAG/UART Adapter, U36 pins configurable as GPIO/UART or other serial interfaces
1Red LED, D10Configuration DONE Led (ON when configuration in progress, OFF when configuration is done)
1User button S2user configurable
1Reset button S1 and pin J2-10low active reset line for FPGA reconfiguration

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JTAG SignalPin on Header J4Note
TCK3-
TDI5-
TDO4-
TMS6-
JTAGEN2-leave floating when use JTAG interface

Table 4: optional JTAG pin header

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chip selectAS_DCLK
Serial Memory U5 PinSignal Schematic NameConnected toNotes
Pin 21, DATA1CSASF_DATA0CSFPGA bank 18, pin H2B3
Data outchip select
Pin 56, DATA0CLKASF_ASDOCLKFPGA bank 1, pin C1A3Data inclock
Pin 15, nCSSI/IO0ASF_NCSDIFPGA bank 1, pin D2A2data in / out
Pin 67, DCLKHOLD/IO3NSTATUS

FPGA bank 1, pin C4

data in / out
Pin 3, WP/IO2DEVCLRNFPGA bank 8, pin H1clockPin 6, DCLKB9data in / out
Pin 2, SO/IO1F_DOFPGA bank 8, pin B2data in / out

Table 5: Serial configuration Quad SPI Flash memory interface connections

SDRAM

The FPGA module is equipped with a Winbond W9864G6JT 64 MBit (8 MByte) SDRAM chip U2. This SDRAM chip is connected to the FPGA bank 7 and 8 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

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