Page History
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| Name / opt. VHD Name | Direction | Pin | Bank Power | Description | Note: PCB REV01 REV02 Connection |
|---|---|---|---|---|---|
| C_TCK | in | 30 | 3.3VIN | JTAG B2B | |
| C_TDI | in | 32 | 3.3VIN | JTAG B2B | |
| C_TDO | out | 1 | 3.3VIN | JTAG B2B | |
| C_TMS | in | 29 | 3.3VIN | JTAG B2B | |
| EN1 | in | 27 | 3.3VIN | Power Enable from B2B Connector (Positive Enable) / Used only for PGOOD feedback | |
| User_LED | out | 4 | 3.3VIN | PS_ERROR_OUTuser defined or status, see ug1085LED description | 1.8V input ERR_OUT(PS_ERROR_OUT) |
| N.C. | 5 | 3.3VIN | / currently_not_used | 1.8V input ERR_STATUS as input | |
| JTAGEN | in | 26 | 3.3VIN | Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access) | |
| MODE | in | 25 | 3.3VIN | Boot Mode for Zynq/ZynqMP Devices (Flash or SD) | |
| MODE0 | out | 12 | 1.8V | ZynqMP Boot Mode Pin 0 | |
| MODE1 | out | 13 | 1.8V | ZynqMP Boot Mode Pin 1 | |
| MODE2 | out | 14 | 1.8V | ZynqMP Boot Mode Pin 2 | |
| MODE3 | out | 16 | 1.8V | ZynqMP Boot Mode Pin 3 | |
| NOSEQ | inout | 23 | 3.3VIN | usage CPLD Variant depends | |
| PGOOD | out | 28 | 3.3VIN | Module Power Good (only Feedback from EN1). | |
| PHY_LED1 | in | 17 | 1.8V | ETH PHY LED1 / currently_not_used | |
| TCK | out | 9 | 1.8V | JTAG ZynqMP | |
| TDI | out | 8 | 1.8V | JTAG ZynqMP | |
| TDO | in | 10 | 1.8V | JTAG ZynqMP | |
| TMS | out | 11 | 1.8V | JTAG ZynqMP | |
| X0 | in | 20 | VCCO_65 | FPGA IO (FPGA Pin H1) / Enable User LED (negative) | output Firmware variant |
| X1 | in | 21 | VCCO_65 | FPGA IO (FPGA Pin J1)/ Connect to User LED | output PHY_LED1 |
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| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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| REV04 | REV03 |
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| v.1 | REV04 | REV03 | John Hartfiel |
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v.1 | REV04 | REV03 |
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| All |
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