Page History

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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation

Overview

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General Design description
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TE0729 Basic-System with Watchdog example via VIO Interface.

Key Features

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Revision History

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Release Notes and Know Issues

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Requirements

Software

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Hardware

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Hardware Support
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Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

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Design supports following carriers:

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Additional HW Requirements:

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Content

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For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

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Overview

TE0729 Basic-System with Watchdog example via VIO Interface.
Refer to http://trenz.org/te0729-info for the current online version of this manual and other available documentation.

Key Features

Revision History

Release Notes and Know Issues

Requirements

Software

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Design supports following carriers:

Additional HW Requirements:

Content

For general structure and of the reference design, see Project Delivery - AMD devices

Design Sources

Additional Sources

Prebuilt

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

• TE0729 "Test Board" Reference Design

Design Flow

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• AMD Development Tools#XilinxSoftware-BasicUserGuides
• Vivado Projects - TE Reference Design
•  Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
   Image Added
2. Press 0 and enter to start "Module Selection Guide"
3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process)
   
   1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see alsoTE Board Part Files
5. Create XSA and export to prebuilt folder
   
   1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
6. Create Linux (uboot.elf and image.ub) with exported XSA
   
   1. XSA is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
   2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
   
   1. "prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
8. Generate Programming Files with Vitis
   
   1. Run on Vivado TCL: TE::sw_run_vitis -all
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
   2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
      Note:  TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis

Launch

Programming

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
2. Press 0 and enter to start "Module Selection Guide"
   1. Select assembly version
   2. Validate selection
   3. Select Create and open delivery binary folder
      Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated

QSPI

Optional for Boot.bin on QSPI Flash and image.ub on SD.

1. Connect JTAG and power on carrier with module
2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
3. Type on Vivado TCL Console: TE::pr_program_flash -swapp u-boot
   Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
             optional "TE::pr_program_flash -swapp hello_te0820" possible
4. Copy image.ub on SD-Card
   • use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
   • or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
5. Insert SD-Card

SD

1. Copy image.ub and Boot.bin on SD-Card
   • use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
   • or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
2. Set Boot Mode to SD-Boot.
   • Depends on Carrier, see carrier TRM.
3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

1. Prepare HW like described on section 105154704
2. Connect UART USB (most cases same as JTAG)
3. Select SD Card as Boot Mode
   Note: See TRM of the Carrier, which is used.
4. Power On PCB
   Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

1. Open Serial Console (e.g. putty)
   
   1. Speed: 115200
   2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
2. Linux Console:
   Note: Wait until Linux boot finished For Linux Login use:
   
   1. User Name: root
   2. Password: root
3. You can use Linux shell now.
   1. I2C 0 Bus type: i2cdetect -y -r 0
   2. I2C 0 Bus type: i2cdetect -y -r 1
   3. ETH0 works with udhcpc
      
   4. ETH1 works with udhcpc
   5. ETH2 works with udhcpc
   6. RTC check: dmesg | grep rtc
   7. USB: insert USB Stick or lsusb
      
4. Option Features
   1. Webserver to get access to Zynq
      1. insert IP on web browser to start web interface
   2. init.sh scripts
      1. add init.sh script on SD, content will be load automatically on startup (template included in ./misc/SD)

Vivado HW Manager

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)

• Control:
  • "WDI_EN" and "WDI_HIT_*_EN_CLK" enables FPGA watchdog control.
  • Force WD to system reboot:
    1. Check on Hardware window VIO status is ok. (right click on vio symbol and click "commit output values to VIO core" for update).
    2. Enable one of the "WDI_HIT_*_EN_CLK" signals
    3. Enable "WDI_EN"
    4. To force system to reboot, disable WDI_HIT clocks.
• Monitoring:
  • Set radix for "fm_*" signals to unsigned integer to see frequ in Hz.
  • "fm_*" shows some clk frequencies (unit Hz). Note: inaccurate Reference CLK is used for frequency measurement.

Scroll Title
anchor Figure_VHM title Vivado Hardware Manager
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System Design - Vivado

Block Design

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anchor Figure_BD title Block Design
Image Added R Variant: Image Added

PS Interfaces

Constrains

Basic module constrains

#
# Common bitgen related settings
#

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
#set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

#
# Set unused pin pullup: PULLNONE, PULLUP, PULLDOWN
#

set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

#set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
#set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDONE [current_design]

Design specific constrain

set_property PACKAGE_PIN F16 [get_ports {FPGA_IO[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_IO[0]}]
set_property PACKAGE_PIN H15 [get_ports {WDI_EN[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {WDI_EN[0]}]
set_property PACKAGE_PIN R15 [get_ports {WD_HIT[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {WD_HIT[0]}]

Software Design - Vitis

For SDK project creation, follow instructions from:

Vitis

Application

Additional Sources

...

Prebuilt

<!-- 

<table width="100%">
<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
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File

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File-Extension

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Description

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Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Add correct path:https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0803/Reference_Design/2017.1/Starterkit
  -->

Reference Design is available on:

• TE0729 "Test Board" Reference Design

Design Flow

<!--
Basic Design Steps
Add/ Remove project specific 
  -->

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• Xilinx Development Tools
• Vivado Projects - TE Reference Design
•  Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
   Image Removed
2. Press 0 and enter for minimum setup
3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
4. Create Project
   
   1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
5. Create HDF and export to prebuilt folder
   
   1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
6. Create Linux (uboot.elf and image.ub) with exported HDF
   
   1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
   2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
         Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
   
   1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
8. Generate Programming Files with HSI/SDK
   
   1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
   2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

Launch

Programming

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Description of Block Design, Constrains...
BD Pictures from Export...
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Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

Optional for Boot.bin on QSPI Flash and image.ub on SD.

1. Connect JTAG and power on carrier with module
2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
   Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
            optional "TE::pr_program_flash_binfile -swapp hello_te0729" possible
4. Copy image.ub on SD-Card
   • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
5. Insert SD-Card

SD

1. Copy image.ub and Boot.bin on SD-Card.
   • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
2. Set Boot Mode to SD-Boot.
   • Depends on Carrier, see carrier TRM.
3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

1. Prepare HW like described on section Programming
2. Connect UART USB (most cases same as JTAG)
3. Select SD Card as Boot Mode
   Note: See TRM of the Carrier, which is used.
4. Power On PCB
   Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

1. Open Serial Console (e.g. putty)
   
   1. Speed: 115200
   2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
2. Linux Console:
   Note: Wait until Linux boot finished For Linux Login use:
   
   1. User Name: root
   2. Password: root
3. You can use Linux shell now.
   1. I2C 0 Bus type: i2cdetect -y -r 0
   2. I2C 0 Bus type: i2cdetect -y -r 1
   3. ETH0 works with udhcpc
      
   4. ETH1 must be configured manually
      1. ifconfig eth1 up
      2. ifconfig eth1 <ip>
   5. ETH1 must be configured manually
      1. ifconfig eth1 up
      2. ifconfig eth1 <ip>
   6. RTC check: dmesg | grep rtc
   7. USB: insert USB Stick or lsusb
      

...

1. Open Vivado Hardware Manager with auto connect.
2. Use probe specification (*.ltx) from prebuilt folder.
3. Add VIO signals to dashboard.
4. Set radix for "fm_*" signals to unsigned integer.
5. "fm_*" shows some clk frequencies (unit Hz). Note: inaccurate Reference CLK is used for frequency measurement.
6. "WDI_EN" and "WDI_HIT_*_EN_CLK" enables FPGA watchdog control.
7. Force WD to system reboot:
   1. Check on Hardware window VIO status is ok. (right click on vio symbol and click "commit output values to VIO core" for update).
   2. Enable one of the "WDI_HIT_*_EN_CLK" signals
   3. Enable "WDI_EN"
   4. To force system to reboot, disable WDI_HIT clocks.

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System Design - Vivado

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Description of Block Design, Constrains...
BD Pictures from Export...
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Block Design

Image Removed

R Variant:

Image Removed

PS Interfaces

...

Constrains

Basic module constrains

#
# Common bitgen related settings
#

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
#set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

#
# Set unused pin pullup: PULLNONE, PULLUP, PULLDOWN
#

set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

#set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
#set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDONE [current_design]

Design specific constrain

set_property PACKAGE_PIN F16 [get_ports {FPGA_IO[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_IO[0]}]
set_property PACKAGE_PIN H15 [get_ports {WDI_EN[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {WDI_EN[0]}]
set_property PACKAGE_PIN R15 [get_ports {WD_HIT[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {WD_HIT[0]}]

Software Design - SDK/HSI

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optional chapter
separate sections for different apps
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For SDK project creation, follow instructions from:

SDK Projects

Application

Source location: \sw_lib\sw_apps

zynqmp_fsbl

TE modified 2018.2 FSBL. Xilinx default FSBL on default setup. eMMC selection with FSBL possible.

Changes:

• Optional define for eMMC selection with FSBL (default SD selected)
  • uncomment #define USE_EMMC on fsbl_hooks.c to select eMMC instead of SD
• See: fsbl_hooks.c, main.c

zynqmp_fsbl_flash

TE modified 2018.2 FSBL

Changes:

...

...

Hello TE0729 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

<!--
optional chapter
Add "No changes." or "Activate: and add List"
   -->

For PetaLinux installation and  project creation, follow instructions from:

• PetaLinux KICKstart

Config

No changes.

U-Boot

Change platform-top.h

...

...

Source location: \sw_lib\sw_apps

zynq_fsbl

TE modified 2019.2 FSBL

General:

• Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)

• Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

• General Changes: 
  
  • Display FSBL Banner and Device ID

Module Specific:

• Add Files: all TE Files start with te_*
  • Optional define for eMMC selection with FSBL (default SD selected)
    • uncomment #define USE_EMMC on fsbl_hooks.c to select eMMC instead of SD

zynq_fsbl_flash

TE modified 2019.2 FSBL

General:

• Modified Files: main.c
• General Changes:
  
  •  Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

hello_te0729

Hello TE0729 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. VitisI is used to generate Boot.bin.

Software Design -  PetaLinux

For PetaLinux installation and  project creation, follow instructions from:

• PetaLinux KICKstart

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

• No changes.

U-Boot

Start with petalinux-config -c u-boot

Changes:

• CONFIG_ENV_IS_NOWHERE=y
• # CONFIG_ENV_IS_IN_SPI_FLASH is not set
• CONFIG_I2C_EEPROM=y
• CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
• CONFIG_SYS_I2C_EEPROM_ADDR=0x50
• CONFIG_SYS_I2C_EEPROM_BUS=0
• CONFIG_SYS_EEPROM_SIZE=256
• CONFIG_SYS_EEPROM_PAGE_WRITE_BITS

...

• =0
• CONFIG_SYS_EEPROM_PAGE_WRITE

...

• _DELAY_MS=0
• CONFIG_SYS_I2C_

...

• EEPROM_ADDR_LEN=1
• CONFIG_SYS_I2C_

...

• EEPROM_ADDR_OVERFLOW=0

Change platform-top.h

Device Tree

Note: for R assembly variant, remove ETH1, ETH2 and RTC

/include/ "system-conf.dtsi"
/ {
  chosen {
    xlnx,eeprom = &eeprom;
  };
};

/* QSPI PHY */
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};



/* ETH PHY */
&gem0 {
    phy-handle = <&phy0>;
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy0: phy@0 {
            compatible = "marvell,88e1510";
            device_type = "ethernet-phy";
            reg = <0>;
        };
    };
};

/* AXI ETH PHY0 */

&axi_ethernetlite_0 {  
    local-mac-address = [00 0a 35 00 22 02];  
    phy-handle = <&phy1>;  
    xlnx,has-mdio = <0x1>;  
    mdio {  
        #address-cells = <1>;  
        #size-cells = <0>;  
        phy1: phy@1 {  
            device_type = "ethernet-phy";  
            reg = <1>;  
        };  
    };  
};

/* AXI ETH PHY1 */
&axi_ethernetlite_1 {  
    local-mac-address = [00 0a 35 00 22 03];  
    phy-handle = <&phy2>;  
    xlnx,has-mdio = <0x1>;  
    mdio {  
        #address-cells = <1>;  
        #size-cells = <0>;  
        phy2: phy@1 {  
            device_type = "ethernet-phy";  
            reg = <1>;  
        };  
    };  
};


/* RTC */
&i2c0 {
    rtc@6F {        // Real Time Clock
       compatible = "isl12022";
       reg = <0x6F>;
    };
  //MAC RealEEPROM
 Time Clock
eeprom: eeprom@50  {
    compatible = "isl12022atmel,24c08";
       reg = <0x6F><0x54>;
   };
};

/* USB PHY */

/{
    usb_phy0: usb_phy@0 {
        compatible = "ulpi-phy";
        //compatible = "usb-nop-xceiv";
        #phy-cells = <0>;
        reg = <0xe0002000 0x1000>;
        view-port = <0x0170>;
        drv-vbus;
    };
};

&usb0 {
    dr_mode = "host";
    //dr_mode = "peripheral";
    usb-phy = <&usb_phy0>;
};

Kernel

Start with petalinux-config -c kernel

ChangesActivate:

• CONFIG_RTC_DRV_ISL12022   (Not needed for R assembly variant, remove)

Rootfs

Activate:

• i2c-tools

• _ISL12022=y

Rootfs

Start with petalinux-config -c rootfs

Changes:

• CONFIG_i2c-tools=y
• CONFIG_busybox-httpd=y (for web server app)
• CONFIG_usbutils=y

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

Additional Software

webfwu

Webserver application accemble for Zynq access. Need busybox-httpd

Core

init-ifupdown

Enable dhcp for ETH1 and ETH2

Additional Software

No additional software is needed.

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