Page History
...
Page properties | ||||
---|---|---|---|---|
| ||||
Template Revision 2.6 8 - on construction Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board" |
...
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
Excerpt |
---|
|
...
Scroll Title | |||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| |||||||||||||||||||||||||||||||||||||||||||
|
...
Scroll Title | ||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||
|
Requirements
Software
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
...
Scroll Title | ||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||
|
Hardware
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
...
Scroll Title | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
...
Scroll Title | |||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| |||||||||||||||||||||||||||
|
Additional Sources
Scroll Title | ||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||
|
...
Page properties | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Notes :
|
...
Scroll Title | |||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| |||||||||||||||||||||||||||||||||||||||||||||
|
...
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
Page properties | ||||
---|---|---|---|---|
| ||||
| ||||
HTML | ||||
<!-- Add correct path/enTE080320171/Starterkit --> |
Reference Design is available on:
Design Flow
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
...
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
- Xilinx AMD Development ToolsTools#XilinxSoftware-BasicUserGuides
- Vivado Projects - TE Reference Design
- Project Delivery.
...
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter to start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
- Create HDF XSA and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
- Generate Programming Files with HSI/SDKVitis
- Run on Vivado TCL: TE::sw_run_hsivitis -all
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_
sdkvitis
Note: TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis
Projects contains 3 FSBL template: zynq_fsbl (FSBL modified for DDR Less application → use for Boot.bin), zynq_fsbl_app (FSBL modified for DDR Less application and with demo app included → create Boot with this FSBL and Bitstream only), zynq_fsbl_flash(FSBL modified for Flash programming →FSBL which must be selected separately to program Flash)See SDK Projects
Info TE0722 is without DDR, so special FSBL (sources on reference designs) is needed, see also: DDR less ZYNQ Design
- Run on Vivado TCL: TE::sw_run_hsivitis -all
...
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debuggingand debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
- Select Create and open delivery binary folder
Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated
QSPI
Optional for Boot.bin on QSPI Flash and image.ub on SD.
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash _binfile -swapp zynq_fsbl_appu-boot
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
optional "TE::pr_program_flash -swapp zynq_fsbl_flash) on setupapp" possible
SD
Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader. Use QSPI for primary boot and SD for secondary boot only. See also Xilinx AR#66846
...
- Prepare HW like described on section 68616275
- Connect UART USB (most cases same as JTAG)
- Power On PCB
Note: 1. Zynq Boot ROM loads FSBL from QSPI into OCM, 2. FSBL loads bitfile from qsiQSPI, 3. FSBL starts application (included into the FSBL Code)
...
Code Block | ||||
---|---|---|---|---|
| ||||
#RGB LED #R set_property PACKAGE_PIN J15 [get_ports {RGB_LED[0]}] #G set_property PACKAGE_PIN L14 [get_ports {RGB_LED[1]}] #B set_property PACKAGE_PIN K12 [get_ports {RGB_LED[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {RGB_LED[*]}] |
Software Design -
...
Vitis
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
For SDK project creation, follow instructions from:SDK Projects
Application
Page properties | ||||
---|---|---|---|---|
| ||||
---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 20182019.3 2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 20182019.3 2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: zynq_fsblTE modified 20182019.3 2 FSBL General:
Module Specific:
zynq_fsbl_flashTE modified 20182019.3 2 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 20182019.3 2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 20182019.3 2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. SDK/HSI Vitis is used to generate Boot.bin. |
Source location: \sw_lib\sw_apps
zynq_fsbl
TE modified 20182019.3 2 FSBL
General:
- Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device ID
- Disable Memory initialisation on main.c
zynq_fsbl_app
TE modified 20182019.3 2 FSBL
General:
- Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device ID
- Disable Memory initialisation on main.c
...
zynq_fsbl_flash
TE modified 20182019.3 2 FSBL
General:
- Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
...
Scroll Title | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
...