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The Trenz Electronic TEC0850 board is a CompactPCI Serial card (3U form factor) integrating a Xilinx Zynq UltraScale+ MPSoC, one DDR4 SDRAM SODIMM socket with 64bit wide data bus, max. dual 512 MByte Flash memory for configuration and operation, 24 Gigabit transceivers on PL side and 4 on PS side, powerful switch-mode power supplies for all onboard voltages, USB2 and USB3 FIFO bridges and a large number of configurable I/Os available on the CompactPCI Serial backplane connectors.

Refer to http://trenz.org/tec0850-info for the current online version of this manual and other available documentation.

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  • Zynq UltraScale+ MPSoC ZU15

  • Front side interface connectors
    • RJ-45 GbE Ethernet interface
    • Circular push/pull connector with 4x on-board 8bit DAC output
    • MicroSD Card connector
    • USB 2.0 and USB 3.0 to FIFO bridge connector
    • 4x status LEDs
  • 4 CompactPCI Serial connectors for backplane connection (3U form factor)
    • 24 GTH lanes
    • 4 PS GTR lanes
    • USB 2.0 interface
    • 64 Zynq PL HP I/O's
    • 8x PLL clock input
    • JTAG, I²C and 7 user I/O's to MAX10 FPGA
  • 64bit DDR4 SODIMM (PS connected), 8 GByte maximum

  • Dual parallel QSPI Flash (bootable), 512 MByte maximum

  • 26-pin header with 20 Zynq PL HD I/O's
  • 3-pin header with 2 MAX10 FPGA I/O's
  • System Controller (Altera MAX10 FPGA SoC)
    • Power Sequencing
    • System management and control for MPSoC and onboard peripherals
  • Si5345 programmable 10 output PLL clock generator
  • Si53340 Quad clock buffer
  • 2x 4bit DIP switches
  • 1x user push button
  • Zynq MPSoC cooling FAN connector
  • On-board high-efficiency DC-DC converters

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Page properties
hiddentrue
idComments

Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on a description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which need carrier us only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

CompactPCI Serial Backplane Connectors

The TEC0850 board is equipped with 3 CompactPCI CompactPCI  Serial high-speed backplane connectors which provide serial high-speed interconnects with transmission rates up to 12 Gb/s to the Zynq MPSoCs MGT lanes. On the cPCI connectors are also available single-ended Zynq MPSoC PL HP I/O's, high-speed USB 2.0 interface and single-ended I/O's of the System Controller FPGA.

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Following diagram gives an overview of the CompactPCI Serial backplane connectors and their connections to the Zynq Ultrascale+ MPSoC and the System Controller FPGA U18:

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Following tables contains information about the interfaces, I/O's, clock and VCCIO sources available on the cPCI connectors:

  1. CompactPCI Serial Connector J1
  2. CompactPCI Serial Connector J3
  3. CompactPCI Serial Connector J4
  4. CompactPCI Serial Connector J5
  5. CompactPCI Serial Connector J6



Anchor
CompactPCI Connector J1
CompactPCI Connector J1

CompactPCI Serial Connector J1


Scroll Title
anchorTable_SIP_cPCI_J1_io
titlecPCI J1 interfaces

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes
I/O1-SC FPGA U18 Bank 6+3V_Dcontrol signals in cPCI pin assignment
6-SC FPGA U18 Bank 8+3V_Dcontrol signals in cPCI pin assignment
I²C2-SC FPGA U18 Bank 1A+3V_DSC FPGA U18 I²C interface
JTAG4-SC FPGA U18 Bank 1A+3V_DSC FPGA U18 JTAG interface
MGT-8 (4 x RX/TX)Bank 502 PS GTR-4x PS GTR lanes
USB2-1 (RX/TX)USB2 PHY U11-USB2 OTG A-Device (host)
Clock Input-1Clock Driver U73-1x Reference clock input from PLL clock U14

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Anchor
CompactPCI Connector J3
CompactPCI Connector J3

CompactPCI Serial Connector J3

CompactPCI Serial connector J3 is not fitted on the TEC0850 board by default, but is necessary if the second optional USB2 PHY U13 if fitted and its USB2 differential serial data interface is connected to the cPCI connector J2. 

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Anchor
CompactPCI Connector J4
CompactPCI Connector J4

CompactPCI Serial Connector J4


Scroll Title
anchorTable_SIP_cPCI_J4_mgt
titlecPCI J4 MGT lanes

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

MGT LaneBankTypeSignal Schematic NamecPCI Connector PinFPGA Pin
0128GTH
  • PE3_RX0_P
  • PE3_RX0_N
  • PE3_TX0_P
  • PE3_TX0_N

J4-D1
J4-E1
J4-A1
J4-B1

MGTHRXP0_128, T33
MGTHRXN0_128, T34
MGTHTXP0_128, T29
MGTHTXN0_128, T30

1128GTH
  • PE3_RX1_P
  • PE3_RX1_N
  • PE3_TX1_P
  • PE3_TX1_N

J4-J1
J4-K1
J4-G1
J4-H1

MGTHRXP1_128, P33
MGTHRXN1_128, P34
MGTHTXP1_128, R31
MGTHTXN1_128, R32

2128GTH
  • PE3_RX2_P
  • PE3_RX2_N
  • PE3_TX2_P
  • PE3_TX2_N

J4-E2
J4-F2
J4-B2
J4-C2

MGTHRXP2_128, N31
MGTHRXN2_128, N32
MGTHTXP2_128, P29
MGTHTXN2_128, P30

3128GTH
  • PE3_RX3_P
  • PE3_RX3_N
  • PE3_TX3_P
  • PE3_TX3_N

J4-K2
J4-L2
J4-H2
J4-I2

MGTHRXP3_128, M33
MGTHRXN3_128, M34
MGTHTXP3_128, M29
MGTHTXN3_128, M30

0129GTH
  • PE4_RX0_P
  • PE4_RX0_N
  • PE4_TX0_P
  • PE4_TX0_N

J4-D3
J4-E3
J4-A3
J4-B3

MGTHRXP0_129, L31
MGTHRXN0_129, L32
MGTHTXP0_129, K29
MGTHTXN0_129, K30

1129GTH
  • PE4_RX1_P
  • PE4_RX1_N
  • PE4_TX1_P
  • PE4_TX1_N

J4-J3
J4-K3
J4-G3
J4-H3

MGTHRXP1_129, K33
MGTHRXN1_129, K34
MGTHTXP1_129, J31
MGTHTXN1_129, J32

2129GTH
  • PE4_RX2_P
  • PE4_RX2_N
  • PE4_TX2_P
  • PE4_TX2_N

J4-E4
J4-F4
J4-B4
J4-C4

MGTHRXP2_129, H33
MGTHRXN2_129, H34
MGTHTXP2_129, H29
MGTHTXN2_129, H30

3129GTH
  • PE4_RX3_P
  • PE4_RX3_N
  • PE4_TX3_P
  • PE4_TX3_N

J4-K4
J4-L4
J4-H4
J4-I4

MGTHRXP3_129, F33
MGTHRXN3_129, F34
MGTHTXP3_129, G31
MGTHTXN3_129, G32

0130GTH
  • PE5_RX0_P
  • PE5_RX0_N
  • PE5_TX0_P
  • PE5_TX0_N

J4-D5
J4-E5
J4-A5
J4-B5

MGTHRXP3_130, B33
MGTHRXN3_130, B34
MGTHTXP3_130, A31
MGTHTXN3_130, A32

1130GTH
  • PE5_RX1_P
  • PE5_RX1_N
  • PE5_TX1_P
  • PE5_TX1_N

J4-J5
J4-K5
J4-G5
J4-H5

MGTHRXP2_130, C31
MGTHRXN2_130, C32
MGTHTXP2_130, B29
MGTHTXN2_130, B30

2130GTH
  • PE5_RX2_P
  • PE5_RX2_N
  • PE5_TX2_P
  • PE5_TX2_N

J4-E6
J4-F6
J4-B6
J4-C6

MGTHRXP1_130, D33
MGTHRXN1_130, D34
MGTHTXP1_130, D29
MGTHTXN1_130, D30

3130GTH
  • PE5_RX3_P
  • PE5_RX3_N
  • PE5_TX3_P
  • PE5_TX3_N

J4-K6
J4-L6
J4-H6
J4-I6

MGTHRXP0_130, E31
MGTHRXN0_130, E32
MGTHTXP0_130, F29
MGTHTXN0_130, F30

0230GTH
  • PE6_RX0_P
  • PE6_RX0_N
  • PE6_TX0_P
  • PE6_TX0_N

J4-D7
J4-E7
J4-A7
J4-B7

MGTHRXP3_230, A4
MGTHRXN3_230, A3
MGTHTXP3_230, A8
MGTHTXN3_230, A7

1230GTH
  • PE6_RX1_P
  • PE6_RX1_N
  • PE6_TX1_P
  • PE6_TX1_N

J4-J7
J4-K7
J4-G7
J4-H7

MGTHRXP2_230, B2
MGTHRXN2_230, B1
MGTHTXP2_230, B6
MGTHTXN2_230, B5

2230GTH
  • PE6_RX2_P
  • PE6_RX2_N
  • PE6_TX2_P
  • PE6_TX2_N

J4-E8
J4-F8
J4-B8
J4-C8

MGTHRXP1_230, C4
MGTHRXN1_230, C3
MGTHTXP1_230, D6
MGTHTXN1_230, D5

3230GTH
  • PE6_RX3_P
  • PE6_RX3_N
  • PE6_TX3_P
  • PE6_TX3_N

J4-K8
J4-L8
J4-H8
J4-I8

MGTHRXP0_230, D2
MGTHRXN0_230, D1
MGTHTXP0_230, E4
MGTHTXN0_230, E3

...

Anchor
CompactPCI Connector J5
CompactPCI Connector J5

CompactPCI Serial Connector J5


Scroll Title
anchorTable_SIP_cPCI_J5_mgt
titlecPCI J5 MGT lanes

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

MGT LaneBankTypeSignal Schematic NamecPCI Connector PinFPGA Pin
0228GTH
  • PE8_RX0_P
  • PE8_RX0_N
  • PE8_TX0_P
  • PE8_TX0_N

J5-D3
J5-E3
J5-A3
J5-B3

MGTHRXP0_228, T2
MGTHRXN0_228, T1
MGTHTXP0_228, R4
MGTHTXN0_228, R3

1228GTH
  • PE8_RX1_P
  • PE8_RX1_N
  • PE8_TX1_P
  • PE8_TX1_N

J5-J3
J5-K3
J5-G3
J5-H3

MGTHRXP1_228, P2
MGTHRXN1_228, P1
MGTHTXP1_228, P6
MGTHTXN1_228, P5

2228GTH
  • PE8_RX2_P
  • PE8_RX2_N
  • PE8_TX2_P
  • PE8_TX2_N

J5-E4
J5-F4
J5-B4
J5-C4

MGTHRXP2_228, M2
MGTHRXN2_228, M1
MGTHTXP2_228, N4
MGTHTXN2_228, N3

3228GTH
  • PE8_RX3_P
  • PE8_RX3_N
  • PE8_TX3_P
  • PE8_TX3_N

J5-K4
J5-L4
J5-H4
J5-I4

MGTHRXP3_228, L4
MGTHRXN3_228, L3
MGTHTXP3_228, M6
MGTHTXN3_228, M5

0229GTH
  • PE7_RX0_P
  • PE7_RX0_N
  • PE7_TX0_P
  • PE7_TX0_N

J5-D1
J5-E1
J5-A1
J5-B1

MGTHRXP0_229, K2
MGTHRXN0_229, K1
MGTHTXP0_229, K6
MGTHTXN0_229, K5

1229GTH
  • PE7_RX1_P
  • PE7_RX1_N
  • PE7_TX1_P
  • PE7_TX1_N

J5-J1
J5-K1
J5-G1
J5-H1

MGTHRXP1_229, J4
MGTHRXN1_229, J3
MGTHTXP1_229, H6
MGTHTXN1_229, H5

2229GTH
  • PE7_RX2_P
  • PE7_RX2_N
  • PE7_TX2_P
  • PE7_TX2_N

J5-E2
J5-F2
J5-B2
J5-C2

MGTHRXP2_229, H2
MGTHRXN2_229, H1
MGTHTXP2_229, G4
MGTHTXN2_229, G3

3229GTH
  • PE7_RX3_P
  • PE7_RX3_N
  • PE7_TX3_P
  • PE7_TX3_N

J5-K2
J5-L2
J5-H2
J5-I2

MGTHRXP3_229, F2
MGTHRXN3_229, F1
MGTHTXP3_229, F6
MGTHTXN3_229, F5

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Anchor
CompactPCI Connector J6
CompactPCI Connector J6

CompactPCI Serial Connector J6


Scroll Title
anchorTable_SIP_cPCI_J6_io
titlecPCI J6 Interfaces

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes
I/O4623PL bank 66PL_1.8V-
189PL bank 65PL_1.8V-
2-SC FPGA U18 Bank 1B+3V_DSignalname: 'DET_RIO', 'DET_BPR'

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Power supply with a minimum current capability of 5A (60W@12V, CompactPCI Serial spec.) for system startup is recommended.

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Scroll Title
anchorTable_RH_DCH
titleDocument change history

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DateRevisionConstributorDescription

Page info
infoTypeModified date
dateFormatyyyy-MM-dd
typeFlat

Page info
infoTypeCurrent version
prefixv.
typeFlat
showVersionsfalse

Page info
infoTypeModified by
typeFlat
showVersionsfalse

  • change" Compact PCI" to "Compact PCI Serial"

v.102Ali Naseri
  • small corrections


v.101


John Hartfiel


  • style changes

v.97Ali Naseri
  • added information about the optional second USB2 PHY and cPCI connector J2 (not fitted by default)

v.94

John Hartfiel

  • small style changes and typo correction

v.93 Ali Naseri , Oleksandr Kiyenko , John Hartfiel
  • initial release
--all

Page info
infoTypeModified users
typeFlat
showVersionsfalse

  • --

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