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Template Revision 2.1 2 - on construction TRM Name always "TE Series Name" +TRM, for example "TE0720 TRM" |
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| anchor | Table_Initial_Delivery_State |
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| title | Table 1: Initial delivery state of programmable devices on the module. |
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Storage device name | Content | Notes |
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.. | .. | .. | | Quad SPI Flash, U5 | DEMO Design | - | | FTDI chip configuration EEPROM, U9 | Programmed | - | OTP Flash area | Empty | Not programmed. |
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Control Signals
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- Overview of Boot Mode, Reset, Enables,
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Signals, Interfaces and Pins
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Notes : - For carrier or stand-alone boards use subsection for every connector typ (add designator on description, not on the subsection title), for example:
- For modules which needs carrier us only classes and refer to B2B connector if more than one is used, for example
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To get started with TEI0010 board, some basic signals are essential and are described in the following table:
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| anchor | Table_Controll_Signals |
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| title | Table 2: TEC0850 Control Signals |
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Control signal | Switch / Button / LED / Pin | Signal Schematic Names | Connected to | Functionality | Notes |
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| MAX10 FPGA U1 JTAGEN | header J4, pin 2 | JTAGEN | MAX10 FPGA U1, bank 1B, pin E5 | high: MAX 10 JTAG enabled,
floating: MAX 10 JTAG disabled | switch the JTAG pins to user GPIO's if drive this pin to GND | | MAX10 FPGA U1 Reset | header J2, pin 10 | RESET | MAX10 FPGA U1, bank 8, pin E7 | low active reset line | also connected to Reset push button S1 | | Supply voltage indicator | Green LED D1 | 3.3V | DCDC U4 | indicating 3.3V voltage level | - | | Configuration DONE indicator | Red LED D10 | CONF_DONE | MAX10 FPGA U1, bank 8, pin C5 | indicating FPGA configuration completed | ON: configuration completed, OFF: FPGA not configured | | Reset Push button | S1 | RESET | MAX10 FPGA U1, bank 8, pin E7 | low active logic | - | | User Push button | S2 | USER_BTN | MAX10 FPGA U1, bank 8, pin E6 | low active logic | available to user |
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Boot Process
The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up.
To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile, means the configuration is lost after power off.
Signals, Interfaces and Pins
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Notes : - For carrier or stand-alone boards use subsection for every connector typ (add designator on description, not on the subsection title), for example:
- For modules which needs carrier us only classes and refer to B2B connector if more than one is used, for example
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I/Os on Pin Headers and Connectors
I/O signals of the FPGA SoC's I/O banks connected to the board's pin headers and connectors:
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| anchor | Table_OV_I/O's |
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| title | General overview of single ended I/O's |
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| Bank | Connector Designator | I/O Signal Count | Bank Voltage | Notes |
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| 2 | J1 | 4 I/O's | 3.3V | - | | J6 | 8 I/O's | Pmod connector | | 5 | J1 | 2 I/O's | 3.3V | - | | J2 | 9 I/O's | 2 I/O's of bank 5 can be pulled-up to 3.3V (4K7 resistors) | | 1B | J4 | JTAG interface and 'JTAGEN' signal (5 I/O's) | 3.3V | JTAG enable signal (JTAGEN) on pin J4-2, switch between user I/O pins and JTAG pin functions | | J3 | 1 I/O | - |
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FPGA I/O banks
Table below contains the signals and interfaces of the FPGA banks connected to pins and peripherals of the board:
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| anchor | Table_OV_I/O's |
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| title | General overview of single ended I/O's |
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| Bank | I/O's Count | Connected to | Notes |
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| 2 | 4 | 1x14 pin header, J1 | user GPIO's | | 8 | Pmod connector, J6 | user GPIO's | | 1 | clock oscillator, U7 | 12.0000 MHz reference clock input | | 1 | reference clock oscillator, U10 | reference clock input from oscillator U10 | | 1 | accelerometer IC, U11 | interrupt 1 line of Analog Devices MEMS accelerometer | | 5 | 9 | 1x14 pin header, J2 | 2 I/O's (D11, D12) of bank 5 can be pulled-up to 3.3V (4K7 resistors) with 1 I/O (D12_R) of same Bank and 1 I/O (D11_R) of bank 6 | | 1 | accelerometer IC, U11 | interrupt 2 line of Analog Devices MEMS accelerometer | | 1 | reference clock oscillator, U10 | oscillator adjustable with three steps of clock output | | 1 | temperature sensor IC, U8 | interrupt line of temperature thresholds | | 6 | 18 | 8 MByte SDRAM 166MHz, U2 | 16bit SDRAM memory interface | | 3 | 22 | 8 MByte SDRAM 166MHz, U2 | 16bit SDRAM memory interface | | 3 | SPI interface connected to IC U8, U11, U12 | SPI interface (MISO, MOSI, MCLK) for temperature sensor U8, 3-axis accelerometer U11 and ADC/DAC U12 | | 1 | temperature sensor IC, U8 | chip-select line for SPI interface | | 1 | accelerometer IC, U11 | chip-select line for SPI interface | | 1 | ADC/DAC IC , U12 | Synchronization line of ACD/DAC IC (active low control input) | | 1 | temperature sensor IC, U8 | interrupt line of critical temperature | | 1A | 8 | 1x14 pin headers J1 | 7 analog inputs or GPIO's, 1 pin analog reference voltage input | | 2 | pin headers J1 | 1 analog inputs or GPIO, 1 dedicated analog input | | 1B | 5 | pin header J4 | 4 I/O's JTAG interface and 1x 'JTAGEN' signal to switch the JTAG pins to user GPIO's if drive this pin to GND | | 8 | 8 | LEDs D2 ... D9 | Red user LEDs | | 6 | QSPI Flash memory, U5 | 6 pins Quad SPI interface, 2 of them pulled up as configuration pins during initialization | | 6 | FTDI FT2232H JTAG/UART adapter, U3 | 6 pins configurable as GPIO/UART or other serial interfaces | | 1 | Red LED, D10 | Configuration DONE Led (ON when configuration in progress, OFF when configuration is done) | | 1 | User button S2 | user configurable | | 1 | Reset button S1 and pin J2-10 | low active reset line for FPGA reconfiguration |
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On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Ethernet PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Subsections...
Power and Power-On Sequence
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