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Main Components
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Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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Notes : - add subsection for every component which is important for design, for example:
- Ethernet PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Subsections...
Power and Power-On Sequence
Power Consumption
Power Distribution Dependencies
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| title | Figure x: Power Distribution |
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Serial Configuration Memory
On-board serial configuration memory (U5) is provided by Winbond W74M64FVSSIQ with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 1 via SPI interface.
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| title | Quad SPI Flash memory interface |
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| Serial Memory U5 Pin | Signal Schematic Name | Connected to | Notes |
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| Pin 1, CS | F_CS | FPGA bank 8, pin B3
| chip select | | Pin 6, CLK | F_CLK | FPGA bank 8, pin A3 | clock | | Pin 5, SI/IO0 | F_DI | FPGA bank 8, pin A2 | data in / out | | Pin 7, HOLD/IO3 | NSTATUS | FPGA bank 8, pin C4 | data in / out (configuration dual-purpose pin of FPGA) | | Pin 3, WP/IO2 | DEVCLRN | FPGA bank 8, pin B9 | data in / out (configuration dual-purpose pin of FPGA) | | Pin 2, SO/IO1 | F_DO | FPGA bank 8, pin B2 | data in / out |
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SDRAM
The FPGA module is equipped with a Winbond W9864G6JT 64 MBit (8 MByte) SDRAM chip U2 in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.
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| SDRAM I/O Signals | Signal Schematic Name | Connected to | Notes |
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| Address inputs | A0 ... A13 | bank 3 | - | Bank address inputs
| BA0 / BA1 | bank 3 | - | | Data input/output | DQ0 ... DQ15 | bank 6 | - | | Data mask | DQM0 ... DQM1 | bank 6 | - | | Clock | CLK | bank 3 |
| | Control Signals | CS | bank 3 | Chip select | CKE | bank 3 | Clock enable | RAS | bank 3 | Row Address Strobe | CAS | bank 3 | Column Address Strobe | | WE | bank 3 | Write Enable |
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FTDI FT2232H Chip
The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.
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| title | FTDI chip interfaces and pins |
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| FTDI Chip U3 Pin | Signal Schematic Name | Connected to | Notes |
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| Pin 12, ADBUS0 | TCK | FPGA bank 1B, pin G2
| JTAG interface | | Pin 13, ADBUS1 | TDI | FPGA bank 1B, pin F5 | | Pin 14, ADBUS2 | TDO | FPGA bank 1B, pin F6 | | Pin 15, ADBUS3 | TMS | FPGA bank 1B, pin G1 | | Pin 32, BDBUS0 | BDBUS0 | FPGA bank 8, pin A4 | user configurable | | Pin 33, BDBUS1 | BDBUS1 | FPGA bank 8, pin B4
| user configurable | | Pin 34, BDBUS2 | BDBUS2 | FPGA bank 8, pin B5 | user configurable | | Pin 35, BDBUS3 | BDBUS3 | FPGA bank 8, pin A6 | user configurable | | Pin 37, BDBUS4 | BDBUS4 | FPGA bank 8, pin B6
| user configurable | | Pin 38, BDBUS5 | BDBUS5 | FPGA bank 8, pin A7 | user configurable |
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ADC/DAC
The TEI0010 board is equipped with the Analog Devices AD5592R 8-channel, 12-bit ADC/DAC which provides eight I/O pins that can be independently configured as digital-to-analog converter (DAC) outputs, analog-to-digital converter (ADC) inputs, digital outputs, or digital inputs. The DAC has a sample frequency up to 50MHz, while ADC and digital GPIO's can be operated at 20MHz.
The ADC/DAC chip has following pin assignment with the FPGA and the board pin-headers, where its I/O pins are available:
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ADC/DAC U12 pin | Signal Schematic Name | Connected to | Notes |
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| Pin 2, I/O0 | AIN0 | header J1, pin 2
| I/O pins configurable
as DAC output, ADC input
or digital GPIOs | | Pin 3, I/O1 | AIN1 | header J1, pin 3
| | Pin 4, I/O2 | AIN2 | header J1, pin 4
| | Pin 5, I/O3 | AIN3 | header J1, pin 5 | | Pin 8, I/O4 | AIN4 | header J1, pin 6
| | Pin 9, I/O5 | AIN5 | header J1, pin 7
| | Pin 10, I/O6 | AIN6 | header J1, pin 8 | | Pin 11, I/O7 | AIN7 | header J3, pin 1 | | Pin 6, VREF | AREF | header J1, pin 1 | Analog I/O's reference voltage.
Note: Internal reference voltage of
2.5V is available on this pin when enabled,
else extern analog reference voltage (range: 1V ... VDD)
has to be applied on this pin. | | Pin 15, nRESET | ADDA_RSTN | FPGA bank 8, pin D6 | IC active low reset pin | | Pin 16, nSYNC | ADDA_SYNC | FPGA bank 3, pin J5 | Frame synchronization signal, data is transferred in
on the falling edge of the next 16 clock cycles. | | Pin 14, SCLK | MCLK | FPGA bank 3, pin J7 | serial clock input | | Pin 13, SDI | MOSI | FPGA bank 3, pin K5 | data input | | Pin 7, SDO | MISO | FPGA bank 3, pin J6 | data output |
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3-Axis MEMS Accelerometer
On the TEI0010 board there is a 3-axis MEMS accelerometer present provided by Analog Devices ADXL362. This accelerometer with 12-bit internal ADC resolution offers many functions to detect motion and has also a temperature sensor integrated. It also has a FIFO buffer for storing output data. The sensor is connected to the FPGA through SPI interface and two interrupt lines.
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| Accelerometer U11 Pin | Signal Schematic Name | Connected to | Notes |
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| Pin 11, INT1 | MEMS_INT1 | FPGA bank 2, pin L2
| Interrupt lines | | Pin 9, INT2 | MEMS_INT2 | FPGA bank 5, pin J9 | | Pin 6, MOSI | MOSI | FPGA bank 3, pin K5 | SPI interface | | Pin 7, MISO | MISO | FPGA bank 3, pin J6 | | Pin 8, nCS | MEMS_CS | FPGA bank 3, pin L5 | | Pin 4, SCLK | MCLK | FPGA bank 3, pin J7 |
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Smoke Detector
The TEI0010 board is equipped with the Analog Devices ADPD188BI optical module for smoke detection. The smoke detector IC has two digital GPIO's, I²C and SPI serial bus as interface for the data output and as control and configuration interface. The smoke detector IC has an integrated 128-byte FIFO buffer for conversed analog values. The values of the internal 14-bit ADC are enhanced for more precision to 20 bits, on 32-bit output register averaged ADC values with a precision of 27 bits are available. For configurable interrupts and timing signals etc., the smoke detector IC offers two GPIO's, which are routed to the FPGA.
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Smoke Detector U14 pin | Signal Schematic Name | Connected to | Notes |
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| Pin 12, SCL | IOM_SCL | FPGA bank 1A, pin F1
| I²C interface | | Pin 13, SDA | IOM_SDA | FPGA bank 1A, pin E1
| | Pin 18, SCLK | ADP_SCK | FPGA bank 1A, pin C2
| SPI interface | | Pin 17, MOSI | ADP_MOSI | FPGA bank 1A, pin C1 | | Pin 16, MISO | ADP_MISO | FPGA bank 1A, pin E4
| | Pin 19, CSB | ADP_CS | FPGA bank 1A, pin B1
| | Pin 14, GPIO0 | IOM_GPIO0 | FPGA bank 1A, pin E3 | GPIO's | | Pin 15, GPIO1 | IOM_GPIO1 | FPGA bank 1A, pin D1 |
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Temperature Sensor
The TEI0010 is equipped with the Analog Devices ADT7320 temperature sensor with SPI interface. The temperature sensor offers a temperature value resolution of 16-bit and high accuracy in temperature measuring. The temperature sensor has two interrupt lines which are configurable to be triggered at a programmable undertemperature/overtemperature or critical temperature value.
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Temperature Sensor U8 pin | Signal Schematic Name | Connected to | Notes |
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| Pin 1, SCLK | MCLK | FPGA bank 3, pin J7
| SPI interface | | Pin 3, DIN | MOSI | FPGA bank 3, pin K5
| | Pin 2, DOUT | MISO | FPGA bank 3, pin J6
| | Pin 4, nCS | TEMP_CS | FPGA bank 3, pin L4 | | Pin 9, INT | TEMP_INT | FPGA bank 5, pin L13
| Interrupt lines | | Pin 10, CT | TEMP_CT | FPGA bank 3, pin N12 |
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System Clock Oscillator
The FPGA SoC module has following reference clocking signals provided by on-board oscillators:
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| Clock Source | Schematic Name | Frequency | Clock Input Destination | Notes |
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| Microchip MEMS Oscillator DSC6011ME2A, U7 | CLK12M | 12.0000MHz | FTDI FT2232 U3, pin 3; FPGA SoC bank 2, pin H6 | - | | Adjustable Oscillator LTC1799CS5, U10 | OSC_CLK | 8.33MHz / 833.33KHz / 83.33KHz | FPGA SoC bank 2, pin G5 | Frequency is set with signal 'OSC_DIV', which is tied
to FPGA bank 5, pin H9. Following settings are available: FPGA pin H9 ('OSC_DIV') open drain: 8.33MHz
FPGA pin H9 ('OSC_DIV') open drain: 833.33KHz
FPGA pin H9 ('OSC_DIV') pulled to 3.3V: 83.33KHz |
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On-board LEDs
There are 10 LEDs fitted on the FPGA module board. The LEDs are user configurable to indicate for example any system status.
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| LED | Color | Signal Schematic Name | FPGA | Notes |
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| D1 | Green | 3.3V | - | Indicating 3.3V board supply voltage | | D2 | Red | 'LED1' | bank 8, pin D8 | user | | D3 | Red | 'LED2' | bank 8, pin A8 | user | | D4 | Red | 'LED3' | bank 8, pin A9 | user | | D5 | Red | 'LED4' | bank 8, pin C9 | user | | D6 | Red | 'LED5' | bank 8, pin A10 | user | | D7 | Red | 'LED6' | bank 8, pin B10 | user | | D8 | Red | 'LED7' | bank 8, pin A11 | user | | D9 | Red | 'LED8' | bank 8, pin C10 | user | | D10 | Red | 'CONF_DONE' | bank 8, pin C5 | indication configuration is DONE when LED is off |
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Push Buttons
The FPGA module is equipped with two push buttons S1 and S2:
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| Button | Signal Schematic Name | FPGA | Notes |
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| S1 | 'USER_BTN' | bank 8, pin E6 | user configurable | | S2 | 'RESET' | bank 8, pin E7 | FPGA reset |
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Connectors
All connectors are are for 100mil headers, all connector locations are in 100mil (2.54mm) grid. The module's PCB provides footprints to mount and solder optional pin headers, if those are not factory-fitted on module.
Power and Power-On Sequence
Power Consumption
To power-up a module, power supply with minimum current capability of 1A is recommended.
Power Supply
The FPGA module can be power-supplied through Micro USB2 connector J9 with supply voltage 'USB-VBUS' or alternative through pin header J2 with supply voltage 'VIN'.
The TEI0010 module needs one single power supply of 5.0V nominal.
There are following dependencies how the initial voltage of the extern power supply is distributed to the on-board DCDC converters:
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Power Consumption
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| FPGA | Design | Typical Power, 25C ambient |
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| Intel MAX 10 10M08 FPGA SoC | Not configured | TBD* |
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*TBD - To Be Determined.
Actual power consumption depends on the FPGA design and ambient temperature.
Power-On Sequence
There is no specific or special power-on sequence, just one single power source is needed.
Power Rails
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| Connector Designator | VCC / VCCIO Schematic Name | Voltage | Direction | Pins | Notes |
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| J2 | 5V | 5.0V | Out | Pin 14 | - | | VIN | 5.0V | In | Pin 13 | - | | 3.3V | 3.3V | Out | Pin 12 | - | | J6 | 3.3V | 3.3V | Out | Pin 6, 12 | - | | J9 | USB_VBUS | 5.0V | In | Pin 1 | - |
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Bank Voltages
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| Voltage | |
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| 2 | 3.3V | all bank voltages fixed | | 3 | 3.3V | | 5 | 3.3V | | 6 | 3.3V | | 1A | 1.8V | | 1B | 3.3V | | 8 | 3.3V |
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Power-On Sequence
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| title | Figure x: Power Sequency |
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Voltage Monitor Circuit
Power Rails
Bank Voltages
Board to Board Connectors
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This section is optional and only for modules.use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors
| Include Page |
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| PD:4 x 5 SoM LSHM B2B Connectors | PD:4 x 5 SoM LSHM B2B Connectors
Technical Specifications
Absolute Maximum Ratings
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| title | Table x: Module absolute maximum ratings. |
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| Parameter | Min | Max | Units | Reference Document |
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Parameter | Min | Max | Units | Reference document |
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VIN supply voltage (5.0V nominal) | -0.3 | 6.0 | V | EP53A7HQI datasheet |
| I/O Input voltage for FPGA I/O bank | -0.5 | 4.12 | V | Intel MAX 10 datasheet |
Storage Temperature | -40 | +90 | °C | LED R6C-AL1M2VY/3T datasheet |
Recommended Operating Conditions
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| title | Table x: Recommended Operating Conditions. |
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| Units | Reference Document | Units | Reference document |
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| VIN supply voltage (5.0V nominal) | 4.75 | 5.25 | V | same as USB-VBUS specification | | I/O Input voltage for FPGA I/O bank | –0.5 | 3.6 | V | Intel MAX 10 datasheet | | Operating temperature range | 0 | +70 | °C | Winbond datasheet W9864G6GT |
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Physical Dimensions
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| title | Figure x: Physical dimensions drawing |
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| title | Table x: Trenz Electronic Shop Overview |
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Hardware Revision History
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| anchor | Table_Module_Absolut_Maximum_RatingsRH_HRH |
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| title | Table x: Module absolute maximum ratings.Hardware Revision History |
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Document Change History
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| title | Table x: Document change history. |
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| Date | Revision | Contributor | Description |
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Create | Modified date | | dateFormat | yyyy-MM-dd |
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