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title	General overview of single ended I/O's

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Bank	Connector Designator	I/O Signal Count	Bank Voltage	Notes
2	J1	4 I/O's	3.3V	-
2	J6	8 I/O's	3.3V	Pmod connector
5	J1	2 I/O's	3.3V	-
5	J2	9 I/O's	3.3V	2 I/O's of bank 5 can be pulled-up to 3.3V (4K7 resistors)
1B	J4	JTAG interface and 'JTAGEN' signal (5 I/O's)	3.3V	JTAG enable signal (JTAGEN) on pin J4-2, switch between user I/O pins and JTAG pin functions
1B	J3	1 I/O	3.3V	-

FPGA I/O banks

Table below contains the signals and interfaces of the FPGA banks connected to pins and peripherals of the board:

JTAG Interface

Primary JTAG access to the FPGA SoC device U1 is provided through Micro USB2 B connector J9. The JTAG interface is created by the FTDI FT2232H USB2 to JTAG/UART adapter IC U3.

Optionally 1x6 male pin header J4 can be fitted on board for access to the JTAG interface between FTDI and FPGA on board. The pin assignment of header J4 is shown on table below:

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title	General overview of single ended I/O'sOptional JTAG pin header

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Bank

I/O's Count

Connected to

Notes

2

4

1x14 pin header, J1

user GPIO's

8

Pmod connector, J6

user GPIO's

1

clock oscillator, U7

12.0000 MHz reference clock input

1

reference clock oscillator, U10

reference clock input from oscillator U10

1

accelerometer IC, U11

interrupt 1 line of Analog Devices MEMS accelerometer

5

9

1x14 pin header, J2

2 I/O's (D11, D12) of bank 5 can be pulled-up to 3.3V (4K7 resistors) with 1 I/O (D12_R) of same Bank and 1 I/O (D11_R) of bank 6

1

accelerometer IC, U11

interrupt 2 line of Analog Devices MEMS accelerometer

1

reference clock oscillator, U10

oscillator adjustable with three steps of clock output

1

temperature sensor IC, U8

interrupt line of temperature thresholds

6

18

8 MByte SDRAM 166MHz, U2

16bit SDRAM memory interface

3

22

8 MByte SDRAM 166MHz, U2

16bit SDRAM memory interface

3

SPI interface connected to IC U8, U11, U12

SPI interface (MISO, MOSI, MCLK) for temperature sensor U8, 3-axis accelerometer U11 and ADC/DAC U12

1

temperature sensor IC, U8

chip-select line for SPI interface

1

accelerometer IC, U11

chip-select line for SPI interface

1

ADC/DAC IC , U12

Synchronization line of ACD/DAC IC (active low control input)

1

temperature sensor IC, U8

interrupt line of critical temperature

1A

8

1x14 pin headers J1

7 analog inputs or GPIO's, 1 pin analog reference voltage input

2

pin headers J1

1 analog inputs or GPIO, 1 dedicated analog input

1B

5

pin header J4

4 I/O's JTAG interface and 1x 'JTAGEN' signal to switch the JTAG pins to user GPIO's if drive this pin to GND

8

LEDs D2 ... D9

Red user LEDs

6

QSPI Flash memory, U5

6 pins Quad SPI interface, 2 of them pulled up as configuration pins during initialization

6

FTDI FT2232H JTAG/UART adapter, U3

6 pins configurable as GPIO/UART or other serial interfaces

1

Red LED, D10

Configuration DONE Led (ON when configuration in progress, OFF when configuration is done)

1

User button S2

user configurable

1

Reset button S1 and pin J2-10

low active reset line for FPGA reconfiguration

On-board Peripherals

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Notes :

add subsection for every component which is important for design, for example:
- Ethernet PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs

Serial Configuration Memory

On-board serial configuration memory (U5) is provided by Winbond W74M64FVSSIQ with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 1 via SPI interface.

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anchor	Table_TS_AMR
title	Quad SPI Flash memory interface

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FPGA bank 8, pin C4

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JTAG Signal	Pin on Header J4	Note
TCK	3	-
TDI	5	-
TDO	4	-
TMS	6	-
JTAGEN	2	leave floating when use JTAG interface, otherwise signals on FPGA are GPIOs

Micro-USB2 Connector

The Micro-USB2 connector J9 provides an interface to access to UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that USB driver is installed on your host PC.

The Digilent plug-in software and cable drivers must be installed on your machine for you to be able to use JTAG interface.

FPGA I/O banks

Table below contains the signals and interfaces of the FPGA banks connected to pins and peripherals of the board:

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title	General overview of single ended I/O's

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Bank	I/O's Count	Connected to	Notes
2	4	1x14 pin header, J1	user GPIO's
	8	Pmod connector, J6	user GPIO's
	1	clock oscillator, U7	12.0000 MHz reference clock input
	1	reference clock oscillator, U10	reference clock input from oscillator U10
	1	accelerometer IC, U11	interrupt 1 line of Analog Devices MEMS accelerometer
5	9	1x14 pin header, J2	2 I/O's (D11, D12) of bank 5 can be pulled-up to 3.3V (4K7 resistors) with 1 I/O (D12_R) of same Bank and 1 I/O (D11_R) of bank 6
	1	accelerometer IC, U11	interrupt 2 line of Analog Devices MEMS accelerometer
	1	reference clock oscillator, U10	oscillator adjustable with three steps of clock output
	1	temperature sensor IC, U8	interrupt line of temperature thresholds
6	18	8 MByte SDRAM 166MHz, U2	16bit SDRAM memory interface
3	22	8 MByte SDRAM 166MHz, U2	16bit SDRAM memory interface
	3	SPI interface connected to IC U8, U11, U12	SPI interface (MISO, MOSI, MCLK) for temperature sensor U8, 3-axis accelerometer U11 and ADC/DAC U12
	1	temperature sensor IC, U8	chip-select line for SPI interface
	1	accelerometer IC, U11	chip-select line for SPI interface
	1	ADC/DAC IC , U12	Synchronization line of ACD/DAC IC (active low control input)
	1	temperature sensor IC, U8	interrupt line of critical temperature
1A	8	1x14 pin headers J1	7 analog inputs or GPIO's, 1 pin analog reference voltage input
1A	2	pin headers J1	1 analog inputs or GPIO, 1 dedicated analog input
1B	5	pin header J4	4 I/O's JTAG interface and 1x 'JTAGEN' signal to switch the JTAG pins to user GPIO's if drive this pin to GND
8	8	LEDs D2 ... D9	Red user LEDs
	6	QSPI Flash memory, U5	6 pins Quad SPI interface, 2 of them pulled up as configuration pins during initialization
	6	FTDI FT2232H JTAG/UART adapter, U3	6 pins configurable as GPIO/UART or other serial interfaces
	1	Red LED, D10	Configuration DONE Led (ON when configuration in progress, OFF when configuration is done)
	1	User button S2	user configurable
	1	Reset button S1 and pin J2-10	low active reset line for FPGA reconfiguration

On-board Peripherals

Page properties

hidden	true
id	Comments

Notes :

add subsection for every component which is important for design, for example:
- Ethernet PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs

Serial Configuration Memory

On-board serial configuration memory (U5) is provided by Winbond W74M64FVSSIQ with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 1 via SPI interface

SDRAM

The FPGA module is equipped with a Winbond W9864G6JT 64 MBit (8 MByte) SDRAM chip U2 in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

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title	16bit SDRAM Quad SPI Flash memory interface

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SDRAM I/O SignalsSerial Memory U5 Pin	Signal Schematic Name	Connected to	Notes
Address inputs	A0 ... A13	bank 3	-
Bank address inputs	BA0 / BA1	bank 3	-
Data input/output	DQ0 ... DQ15	bank 6	-
Data mask	DQM0 ... DQM1	bank 6	-
Clock	CLK	bank 3
Control Signals	CS	bank 3	Chip select
	CKE	bank 3	Clock enable
	RAS	bank 3	Row Address Strobe
	CAS	bank 3	Column Address Strobe
	WE	bank 3	Write Enable

FTDI FT2232H Chip

Pin 1, CS	F_CS	FPGA bank 8, pin B3	chip select
Pin 6, CLK	F_CLK	FPGA bank 8, pin A3	clock
Pin 5, SI/IO0	F_DI	FPGA bank 8, pin A2	data in / out
Pin 7, HOLD/IO3	NSTATUS	FPGA bank 8, pin C4	data in / out (configuration dual-purpose pin of FPGA)
Pin 3, WP/IO2	DEVCLRN	FPGA bank 8, pin B9	data in / out (configuration dual-purpose pin of FPGA)
Pin 2, SO/IO1	F_DO	FPGA bank 8, pin B2	data in / out

SDRAM

The FPGA module is equipped with a Winbond W9864G6JT 64 MBit (8 MByte) SDRAM chip U2 in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

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title	16bit SDRAM memory interface

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SDRAM I/O Signals	Signal Schematic Name	Connected to	Notes
Address inputs	A0 ... A13	bank 3	-
Bank address inputs	BA0 / BA1	bank 3	-
Data input/output	DQ0 ... DQ15	bank 6	-
Data mask	DQM0 ... DQM1	bank 6	-
Clock	CLK	bank 3
Control Signals	CS	bank 3	Chip select
	CKE	bank 3	Clock enable
	RAS	bank 3	Row Address Strobe
	CAS	bank 3	Column Address Strobe
	WE	bank 3	Write Enable

FTDI FT2232H Chip

The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

Warning
Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license, the onboard JTAG will not be accessible anymore with any Xilinx tools. Software tools from the FTDI website do not warn or ask for confirmation before erasing user EEPROM content.

Channel A of the FTDI IC is configured as JTAG interface (MPSSE) connected to the MAX10 FPGA U1.

Channel B can be used as UART Interface routed to the MAX10 FPGA U1The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are is routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs , UART or and other standard interfaces.The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

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title	FTDI chip interfaces and pins

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FTDI Chip U3 Pin	Signal Schematic Name	Connected to	Notes
Pin 12, ADBUS0	TCK	FPGA bank 1B, pin G2	JTAG interface
Pin 13, ADBUS1	TDI	FPGA bank 1B, pin F5
Pin 14, ADBUS2	TDO	FPGA bank 1B, pin F6
Pin 15, ADBUS3	TMS	FPGA bank 1B, pin G1
Pin 32, BDBUS0	BDBUS0	FPGA bank 8, pin A4	user configurable
Pin 33, BDBUS1	BDBUS1	FPGA bank 8, pin B4	user configurable
Pin 34, BDBUS2	BDBUS2	FPGA bank 8, pin B5	user configurable
Pin 35, BDBUS3	BDBUS3	FPGA bank 8, pin A6	user configurable
Pin 37, BDBUS4	BDBUS4	FPGA bank 8, pin B6	user configurable
Pin 38, BDBUS5	BDBUS5	FPGA bank 8, pin A7	user configurable

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Trenz Electronic Documentation

Versions Compared

Old Version 15

New Version 16

Key

FPGA I/O banks

JTAG Interface

On-board Peripherals

Serial Configuration Memory

Micro-USB2 Connector

FPGA I/O banks

On-board Peripherals

Serial Configuration Memory

SDRAM

FTDI FT2232H Chip

SDRAM

FTDI FT2232H Chip