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Scroll Title
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titleBoot process.

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Signal

DesignatorB2BSignal LevelBoot Mode

Boot_R

J4

J2-11

Open

QSPI

ShortSD Card


Reset Process

There is a user push button which is used for RESET signal.

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titleReset process.

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Signal

DesignatorB2BActive Level

RESET

S1

J2-7

Active High



Signals, Interfaces and Pins

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Scroll Title
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titleGeneral PL I/O to B2B connectors information

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B2B ConnectorInterfacesNumber of I/ONotes
J1

User I/O48 singel ended, 24 differentialConnected to Bank 13
4 Single endedMIO10-13
CANH , CANL2 single endedMIO8, MIO9
J2

User I/O22 singel ended, 11 differential
38 single endedMIO16-53
SoM Control Signals5RESET, RST_OUT, BOOT_R,
JTAG Interface4TCK , TDO, TDI, TMS

J3


User I/O20 Single ended, 10 differential


Connected to Bank 35
34 single ended, 17 differentialConnected to Bankd 33
Ethernet 14 single ended, 2 differentialETH_CTREF , ETH_TD+, ETH_TD- , ETH_RD+, ETH_RD-, ETH_LED1, ETH_LED2, ETH_LED3
Ethernet 24 single ended, 2 differentialETH_CTREF , ETH_TD+, ETH_TD- , ETH_RD+, ETH_RD-, ETH_LED1, ETH_LED2, ETH_LED3


On-board Connector

Scroll Title
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titleGeneral PL I/O to B2B connectors information

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B2B ConnectorInterfacesNumber of I/ONotes
J5

User I/O48 singel ended, 24 differentialConnected to Bank 13
34 single ended, 17 differentialConnected to Bank 33
J6

User I/O42 singel ended, 21 differential
27 single endedMIO16
-39
... MIO39 + MIO 51-53
4 single endedMIO10-13
SoM Control Signals3RESET, RST_OUT, BOOT_R
JTAG Interface4TCK , TDO, TDI, TMS

CANH , CANL

2 single endedMIO8 , MIO9


JTAG Interface

JTAG access to the Xilinx XXXXXXX FPGA TE0728 Trenz Module through B2B connector JM2J2.

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titleJTAG pins connection

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JTAG Signal

B2B Pin

TMSJ2-12
TDIJ2-10
TDOJ2-8
TCKJ2-6



On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

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Scroll Title
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titleOn board peripherals

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SignalsConnected toB2BNotes
CD/DAT3MIO45J2-31
CMDMIO41J2-29
CLKMIO40_CLKJ2-34
DAT0MIO42J2-37
DAT1MIO43J2-40
DAT2MIO44J2-32
CDMIO46J2-35
WPMIO47J2-33


RJ45 Connector

Scroll Title
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titleQuad SPI interface MIOs and pins

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Signal ETH1B2BSignal ETH2B2BNotes
ETH1_TD+J3-58ETH2_TD+J3-28Transfer
ETH1_TD-J3-56ETH2_TD-J3-26
ETH1_RD+J3_52ETH2_RD+J3-22Receive
ETH1_RD-J3-50ETH2_RD-J3-20
ETH1_CTREFJ3_57ETH2_CTREFJ3-25
ETH1_LED1J3-55ETH2_LED1J3-23Yellow - Activity
ETH1_LED3J3-51ETH2_LED3J3-19Green - Link


LEDs

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Schematic
DesignatorColorConnected toB2BActive Level
IO Standard

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RESET_N
Note
D1-ARedMIO48J2-30Active high
D1-BYellowMIO49J2-38Active high
D1-CGreenMIO50J2-36Active high
Scroll Title
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titleEthernet PHY to Zynq SoC connections
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SchematicETH1ETH2PullupNotes
CTREFTD+TD-RD+RD-LED1LED2LED3POWERDOWN/INT



Power and Power-On Sequence

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