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Board to Board (B2B) I/Os

FPGA bank number and number Number of I/O signals FPGA bank numbers connected to the B2B connectorconnectors:

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titleGeneral PL I/O to B2B connectors information

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B2B ConnectorInterfacesNumber of I/ONotes
J1

User I/O48 singel ended, 24 differentialConnected to Bank 13
4 Single endedMIO10-13
CANH , CANL2 single endedMIO8, MIO9
J2

User I/O22 singel ended, 11 differential
38 single endedMIO16-53
SoM Control Signals5RESET, RST_OUT, BOOT_R,
JTAG Interface4TCK , TDO, TDI, TMS

J3


User I/O20 Single ended, 10 differential


Connected to Bank 35
34 single ended, 17 differentialConnected to Bankd 33
Ethernet 14 single ended, 2 differentialETH_CTREF , ETH_TD+, ETH_TD- , ETH_RD+, ETH_RD-, ETH_LED1, ETH_LED2, ETH_LED3
Ethernet 24 single ended, 2 differentialETH_CTREF , ETH_TD+, ETH_TD- , ETH_RD+, ETH_RD-, ETH_LED1, ETH_LED2, ETH_LED3


On-board Connector

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B2B ConnectorInterfacesNumber of I/ONotes
J5

User I/O48 singel ended, 24 differentialConnected to Bank 13
34 single ended, 17 differentialConnected to Bank 33
J6

User I/O42 singel ended, 21 differential
27 single endedMIO16... MIO39 + MIO 51-53
4 single endedMIO10-13
SoM Control Signals3RESET, RST_OUT, BOOT_R
JTAG Interface4TCK , TDO, TDI, TMS

CANH , CANL

2 single endedMIO8 , MIO9


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titleJTAG pModeMode

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S2ONOFFDefaultDescription
1Normal modeAdapter board CPLD update modeONUpdate Mode JTAG access to SC CPLD only
2Do not use (illegal setting)Normal modeOFFMust be in OFF state always.
3VIO connected to 3.3VPower VIO from pin header J2OFFUser I/O Voltage
4Power 3.3V from USBPower 3.3V from pin header J2OFFPower on-board peripherals (FTDI chip & SC CPLD, ...)


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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

SD Card Socket

VDD for SD card holder is 3.3V.

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titleOn board peripherals

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SignalsConnected toB2BNotes
CD/DAT3MIO45J2-31
CMDMIO41J2-29
CLKMIO40_CLKJ2-34
DAT0MIO42J2-37
DAT1MIO43J2-40
DAT2MIO44J2-32
CDMIO46J2-35
WPMIO47J2-33


...

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titleQuad SPI interface MIOs and pins

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Signal ETH1B2BSignal ETH2B2BNotes
ETH1_TD+J3-58ETH2_TD+J3-28Transfer
ETH1_TD-J3-56ETH2_TD-J3-26
ETH1_RD+J3_52ETH2_RD+J3-22Receive
ETH1_RD-J3-50ETH2_RD-J3-20
ETH1_CTREFJ3_57ETH2_CTREFJ3-25
ETH1_LED1J3-55ETH2_LED1J3-23Yellow LED- Activity
ETH1_LED3J3-51ETH2_LED3J3-19Green Green- Link

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Push button

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titleOn-board LEDspush button

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DesignatorColorConnected toB2BActive LevelNote
D1-AS1RedRESETMIO48J2-307Active highGeneral Input RESET



LEDs

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DesignatorColorConnected toB2BActive LevelNote
D1-ARedMIO48J2-30Active high
D1-BYellowMIO49J2-38Active D1-BYellowMIO49J2-38Active high
D1-CGreenMIO50J2-36Active high



Power and Power-On Sequence

Power Supply

Power Single 12V power supply with minimum current capability of 3.5 A for system startup 5A is recommended to operate the board.

Power Consumption

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Power Input PinTypical Current
VIN

TBD*

VBATT

TBD*



* TBD - To Be Determined

Power Distribution Dependencies

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titlePower Distribution


add drawIO object here: Attention if you copy from other page, objects are only linked.
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