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Template Revision 2.2 - on construction

Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"

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Template Revision 1.4.1
Basic Notes
 - export PDF to download, if vivado revision is changed!
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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation
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Table of contents

Table of Contents
outlinetrue

Overview

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General Design description
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Design example with Linux and MGT-CLK frequency monitoring over VIO.

Key Features

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Excerpt
  • PetaLinux
  • SD
  • ETH
  • USB
  • I2C
  • PCIe
  • DP
  • FMeter
  • LED
  • Modified FSBL for SI5338 and SI5345 programming
  • Special FSBL for QSPI programming

Revision History

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- Add changes from design
- Export PDF to download, if vivado revision is changed!
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  • initial release

Release Notes and Know Issues

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Requirements

Software

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Hardware

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Hardware Support
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Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

...

  • reduced DDR speed for ES Variant
  • Xilinx has stopped ES1 support with 2018.2, please use 2017.1 reference design

...

Additional HW Requirements:

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Content

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For general structure and of the reference design, see Project Delivery

Design Sources

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Additional Sources

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Prebuilt

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<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
</table>
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Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template (note: inner scroll ignore/only only with drawIO object):

        Scroll Title
        anchorFigure_xyz
        titleText
        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use

        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)
      • Scroll Title
        anchorTable_xyz
        titleText

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefault
        style
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        sortByColumn1
        sortEnabledfalse
        cellHighlightingtrue

        ExampleComment
        12
  • ...
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Table of contents

Table of Contents
outlinetrue

Overview

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Notes :


Design example with Linux and MGT-CLK frequency monitoring over VIO.

Refer to http://trenz.org/teb0911-info for the current online version of this manual and other available documentation.

Key Features

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Notes :

  • Add basic key futures, which can be tested with the design
Excerpt
  • PetaLinux
  • SD
  • ETH
  • USB
  • I2C
  • PCIe
  • DP
  • FMeter
  • LED
  • Modified FSBL for SI5338 and SI5345 programming
  • Special FSBL for QSPI programming

Revision History

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Notes :

  • add every update file on the download
  • add design changes on description
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DateVivadoProject BuiltAuthorsDescription
2018-11-262018.2TEB0911-test_board_noprebuilt-vivado_2018.2-build_03_20181126132622.zip
TEB0911-test_board-vivado_2018.2-build_03_20181126132607.zip
John Hartfiel
  • new assembly variant
  • add init.sh
2018-07-202018.2TEB0911-test_board_noprebuilt-vivado_2018.2-build_02_20180719153443.zip
TEB0911-test_board-vivado_2018.2-build_02_20180719153429.zip
John Hartfiel
  • initial release

Release Notes and Know Issues

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Notes :
  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if  issue fixed
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titleKnown Issues

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IssuesDescriptionWorkaroundTo be fixed version
No known issues---------

Requirements

Software

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Notes :

  • list of software which was used to generate the design
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titleSoftware

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SoftwareVersionNote
Vivado2018.2needed
SDK2018.2needed
PetaLinux2018.2needed
SI5338 Clock Builder---optional
SI5345 Clock Builder Pro---optional

Hardware

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Notes :

  • list of software which was used to generate the design


Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Scroll Title
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titleHardware Modules

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Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashOthersNotes
TEB0911-01-ES1es1REV02, REV01SODIMM, configured for 4GB: KVR24S17S8/864MB
  • reduced DDR speed for ES Variant
  • Xilinx has stopped ES1 support with 2018.2, please use 2017.1 reference design
TEB0911-04-09EG-1E9eg_1eREV04, REV03, REV02SODIMM, configured for 8GB: CT8G4SFS824A64MB

TEB0911-04-15EG-1E15eg_1eREV04SODIMM, configured for 8GB: CT8G4SFS824A64MB

Additional HW Requirements:

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titleAdditional Hardware

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Additional HardwareNotes


Content

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  • content of the zip file


For general structure and of the reference design, see Project Delivery

Design Sources

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TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration

Additional Sources

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titleAdditional design sources

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TypeLocationNotes
SI5338<design name>/misc/Si5338SI5338 Project with current PLL Configuration
SI5345<design name>/misc/Si5345SI5345 Project with current PLL Configuration
init.sh<design name>/misc/init_scriptAdditional Initialization Script for Linux

Prebuilt

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  • prebuilt files
  • Template Table:
    • Scroll Title
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      titlePrebuilt files

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      File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems

Scroll Title
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titlePrebuilt files (only on ZIP with prebult content)

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repeatTableHeadersdefault
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File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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  • Important set new Vivado version link on every Design update of new vivado version!
  • Set Link to download folder (Remove ../de/.. ../en/.. from url) for example: https://shop.trenz-electronic.de
/enTE080320171/Starterkit   -->


Reference Design is available on:

Design Flow

<!-- Basic Design Steps Add/ Remove project specific   -->
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Notes :
  • Basic Design Steps

  • Add/ Remove project specific description

Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

...

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
  2. Press 0 and enter for minimum setup
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project
    1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (uboot.elf and image.ub) with exported HDF
    1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
        Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
  7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
  8. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

Launch

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Note:

  • Programming and Startup procedure

Programming

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Check Module and Carrier TRMs for proper HW
Note
Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

...

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
    Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
             Optional "TE::pr_program_flash_binfile -swapp hello_te0803teb0911" possible
  4. Copy image.ub and optional misc/sd/init.sh on SD-Card
    • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  5. Insert SD-Card

SD

  1. Copy image.ub and , Boot.bin and misc/sd/init.sh on SD-Card.
    • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  2. Set Boot Mode to SD-Boot.
  3. Insert SD-Card in SD-Slot.

...

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
  3. You can use Linux shell now.
    1. I2C 0 Bus type: i2cdetect -y -r 0
    2. ETH0 works with udhcpc
    3. USB type  "lsusb" or connect USB device
    4. PCIe type "lspci"

Vivado HW Manager

(coming soon)

System Design - Vivado

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Block Design

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PS Interfaces

Activated interfaces:

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Constrains

Basic module constrains

Code Block
languageruby
title_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

...

languageruby
title_i_TEB0911.xdc

...


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Note:

  • Add picture of HW Manager

  • add notes for the signal either groups or topics, for example:

    Control:

    • add controllable IOs with short notes..

    Monitoring:

    • add short notes for signals which will be monitored only

    SI5338_CLK0 Counter: 

    Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz

Control:

  • User LED Control (D16, D15)

Monitoring:

  • MGT CLK Measurement:
    • Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz
    • Default B229_CLK1: 78,8MHz, B128_CLK1: 150MHz, B129_CLK1: 175MHz, B130_CLK1: 200MHz, B228_CLK1: 125MHz, B23ß_CLK1: 100MHz


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titleVivado Hardware Manager
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System Design - Vivado

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Note:

  • Description of Block Design, Constrains... BD Pictures from Export...



Block Design

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titleBlock Design
Image Added


PS Interfaces

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Note:

  • optional for Zynq / ZynqMP only

  • add basic PS configuration

Activated interfaces:

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titlePS Interfaces

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TypeNote
DDRSODIMM, setting depends on used memory
QSPIMIO
SD0MIO
SD1MIO
I2C0MIO
PJTAG0MIO
UART0MIO
GPIO0MIO
SWDT0..1
TTC0..3
GEM3MIO
USB0MIO/GTP
PCIeMIO/GTP
DisplayPortEMIO/GTP
TypNot
DDRSODIMM, setting depends on used memory
QSPIMIO
SD0MIO
SD1MIO
I2C0MIO
PJTAG0MIO
UART0MIO
GPIO0MIO
SWDT0..1
TTC0..3
GEM3MIO
USB0MIO/GTP
PCIeMIO/GTP
DisplayPortEMIO/GTP


Constrains

Basic module constrains

Code Block
languageruby
title_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

Code Block
languageruby
title_i_TEB0911.xdc
# GT Clocks
#B128-1
set_property PACKAGE_PIN N27 [get_ports {PL_MGT_CLK_clk_p[50]}]

## DP#B129-1
set_property PACKAGE_PIN AB1J27 [get_ports dp_aux_data_in]
{PL_MGT_CLK_clk_p[1]}]
#B228-1
set_property PACKAGE_PIN J8 V9 [get_ports dp{PL_hotMGT_plug_detect]CLK_clk_p[2]}]
#B130-1
set_property PACKAGE_PIN AA8E27 [get_ports dp_aux_data_out]
{PL_MGT_CLK_clk_p[3]}]
#B229-1
set_property PACKAGE_PIN AA3E8  [get_ports dp{PL_auxMGT_dataCLK_oe_n]clk_p[4]}]
#B230-1
set_property IOSTANDARDPACKAGE_PIN LVCMOS18B10 [get_ports dp_*{PL_MGT_CLK_clk_p[5]}]

## LEDDP
set_property PACKAGE_PIN K14AB1 [get_ports {LED[0]}]
set_dp_aux_data_in]
set_property PACKAGE_PIN K10V9 [get_ports {LED[1]}]dp_hot_plug_detect]
set_property IOSTANDARDPACKAGE_PIN LVCMOS18AA8 [get_ports {LED*}]


Software Design - SDK/HSI

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For SDK project creation, follow instructions from:

SDK Projects

Application

SDK template in ./sw_lib/sw_apps/ available.

zynqmp_fsbl

TE modified 2018.2 FSBL

Changes:

  • Si5345Configuration
    •  see xfsbl_board.c and xfsbl_board.h, xfsbl_main.c
    • Add Si5345-Registers.h, si5345.c, si5345.h, si5338.c, si5338.h, register_map.h

Note: Remove compiler flags "-Os -flto -ffat-lto-objects" on 2018.2 SDK to generate FSBL

...

dp_aux_data_out]
set_property PACKAGE_PIN AA3  [get_ports dp_aux_data_oe_n]
set_property IOSTANDARD LVCMOS18 [get_ports dp_*]
## LED
set_property PACKAGE_PIN K14 [get_ports {LED[0]}]
set_property PACKAGE_PIN K10 [get_ports {LED[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {LED*}]


Software Design - SDK/HSI

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Note:
  • optional chapter separate

  • sections for different apps


For SDK project creation, follow instructions from:

SDK Projects

Application

SDK template in ./sw_lib/sw_apps/ available.

zynqmp_fsbl

TE modified 2018.2 FSBL

Changes:

  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

...

  • Si5345Configuration
    •  see xfsbl_board.c and xfsbl_board.h, xfsbl_main.c
    • Add Si5345-Registers.h, si5345.c, si5345.h, si5338.c, si5338.h, register_map.h

Note: Remove compiler flags "-Os -flto -ffat-lto-objects" on 2018.2 SDK to generate FSBL

zynqmp_

...

Xilinx default PMU firmware.

hello_teb0911

Hello TEB0911 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

...

fsbl_flash

TE modified 2018.2 FSBL

Changes:

  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

Note: Remove compiler flags "-Os -flto -ffat-lto-objects" on 2018.2 SDK to generate FSBL

zynqmp_pmufw

Xilinx default PMU firmware.

hello_teb0911

Hello TEB0911 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

...

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Note:
  • optional chapter separate

  • sections for linux

  • Add "No changes." or "Activate: and add List"


For PetaLinux installation and  project creation, follow instructions from:

...

Code Block
languagejs
/include/ "system-conf.dtsi"
/ {
};

/* USB  */

&dwc3_0 {
    status = "okay";
    dr_mode = "host";
};


/* QSPI */

&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};



/* ETH */

&gem3 {
        phy-handle = <&phy0>;
        phy0: phy0@1 {
                device_type = "ethernet-phy";
                reg = <1>;
        };
};



/* SD1 */

&sdhci1 {
    // disable-wp;
    no-1-8-v;

};


&i2c0 {
    i2cswitch@76 { // I2C Switch U13
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x76>;
        i2c-mux-idle-disconnect;

        i2c@2 { // FMCD (/dev/i2c-3)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <2>;
        };
        i2c@3 { // FMCE (/dev/i2c-4)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;
        };
        i2c@4 { // FMCB (/dev/i2c-5)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <4>;
        };
        i2c@5 { // FMCC (/dev/i2c-6)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <5>;
        };
        i2c@6 { // PLL (/dev/i2c-7)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <6>;

            si570_2: clock-generator3@5d {
                #clock-cells = <0>;
                compatible = "silabs,si570";
                reg = <0x5d>;
                temperature-stability = <50>;
                factory-fout = <156250000>;
                clock-frequency = <78800000>;

            };
        };
    };
    i2cswitch@77 { // I2C Switch U37
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x77>;
        i2c-mux-idle-disconnect;

        i2c@0 { // SFP2 (/dev/i2c-9)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0>;
        };
        i2c@1 { // FMCA (/dev/i2c-10)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>;
        };
        i2c@2 { // FMCF (/dev/i2c-11)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <2>;
        };
        i2c@3 { // SFP0 (/dev/i2c-12)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;
        };
        i2c@4 { // SFP1 (/dev/i2c-13)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <4>;
        };
        i2c@5 { // MEM (/dev/i2c-14)
            // Low frequency to work with CPLD
            clock-frequency = <100000>;
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <5>;
        };
        i2c@6 { // DDR4 (/dev/i2c-15)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <6>;
        };
        i2c@7 { // USBH (/dev/i2c-16)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <7>;
        };

    };
};

/* UNUSED DMA disable */

&lpd_dma_chan1 {
    status = "disabled";
};
&lpd_dma_chan2 {
    status = "disabled";
};
&lpd_dma_chan3 {
    status = "disabled";
};
&lpd_dma_chan4 {
    status = "disabled";
};
&lpd_dma_chan5 {
    status = "disabled";
};
&lpd_dma_chan6 {
    status = "disabled";
};
&lpd_dma_chan7 {
    status = "disabled";
};
&lpd_dma_chan8 {
    status = "disabled";
};



Kernel

Deactivate:

  • CONFIG_CPU_IDLE      (only needed to fix JTAG Debug issue)

  • CONFIG_CPU_FREQ    (only needed to fix JTAG Debug issue)

Rootfs

Activate:

  • i2c-tools

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

Additional Software

HTML
<!--
Add Description for other Software, for example SI CLK Builder ...
 -->

No additional software is needed.

SI5338

Download  ClockBuilder Desktop for SI5338

  1. Install and start ClockBuilder
  2. Select SI5338
  3. Options → Open register map file
    Note: File location <design name>/misc/Si5338/RegisterMap.txt
  4. Modify settings
  5. Options → save C code header files
  6. Replace Header files from FSBL template with generated file

SI5345

Download  ClockBuilder Pro for SI5345

  1. Install and start ClockBuilder
  2. Open "/misc/SI5345/Si5345-RevB-0808-02A-Project.slabtimeproj"
  3. Modify settings
  4. Export → Register File → select C code header → save to file
  5. Replace Header files from FSBL template with generated file

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

HTML
<!--
Generate new entry:
1:add new row below first
2:Copy Page Information Macro(date+user) Preview, Page Information Macro Preview
3.Update Metadate =Page Information Macro Preview+1
  -->

...


};



Kernel

Deactivate:

  • CONFIG_CPU_IDLE      (only needed to fix JTAG Debug issue)

  • CONFIG_CPU_FREQ    (only needed to fix JTAG Debug issue)

Rootfs

Activate:

  • i2c-tools

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files


Additional Software

Page properties
hiddentrue
idComments
Note:
  • Add description for other Software, for example SI CLK Builder ...
  • SI5338 and SI5345 also Link to:

No additional software is needed.

SI5338

File location <design name>/misc/Si5338/RegisterMap.txt

General documentation how you work with these project will be available on Si5338

SI5345

File location <design name>/misc/Si5345/Si5345-RevD-0911-Project.slabtimeproj

General documentation how you work with these project will be available on Si5345

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

Page properties
hiddentrue
idComments
  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports

...

Scroll Title
anchorTable_dch
titleDocument change history.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths2*,*,3*,4*
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DateDocument Revision

Authors

Description

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
typeFlat

Page info
infoTypeModified by
dateFormatyyyy-MM-dd
type

...

Flat

  • new assembly variant
  • documentation style update

v.

...

4John Hartfiel
  • 2018.

...

  • 2 release
2018-07-20v.1

...

  • Initial release

...

John Hartfiel
  • Initial release
--all

Page info

...

infoTypeModified users
dateFormatyyyy-MM-dd
typeFlat

--

Legal Notices

Include Page
IN:Legal Notices
IN:Legal Notices

...