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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation

Overview

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General Design description
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Design example with Linux and MGT-CLK frequency monitoring over VIO.

Key Features

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Revision History

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• initial release

Release Notes and Know Issues

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Requirements

Software

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Hardware

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Hardware Support
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Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

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• reduced DDR speed for ES Variant
• Xilinx has stopped ES1 support with 2018.2, please use 2017.1 reference design

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Additional HW Requirements:

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Content

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For general structure and of the reference design, see Project Delivery

Design Sources

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Overview

Design example with Linux and MGT-CLK frequency monitoring over VIO.

Refer to http://trenz.org/teb0911-info for the current online version of this manual and other available documentation.

Key Features

Revision History

Release Notes and Know Issues

Requirements

Software

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Additional HW Requirements:

Content

For general structure and of the reference design, see Project Delivery

Design Sources

Additional Sources

Prebuilt

Additional Sources

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Prebuilt

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<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
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Description

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Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

• TEB0911 "Test Board" Reference Design

Design Flow

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1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
   
2. Press 0 and enter for minimum setup
3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
4. Create Project
   
   1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
5. Create HDF and export to prebuilt folder
   
   1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
6. Create Linux (uboot.elf and image.ub) with exported HDF
   
   1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
   2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
         Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
   
   1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
8. Generate Programming Files with HSI/SDK
   
   1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
   2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

Launch

Programming

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1. Connect JTAG and power on carrier with module
2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
   Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
            Optional "TE::pr_program_flash_binfile -swapp hello_te0803teb0911" possible
4. Copy image.ub and optional misc/sd/init.sh on SD-Card
   • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
5. Insert SD-Card

SD

1. Copy image.ub and , Boot.bin and misc/sd/init.sh on SD-Card.
   • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
2. Set Boot Mode to SD-Boot.
   • Depends on CPLD Firmware, see SC0911 CPLD#BootMode
3. Insert SD-Card in SD-Slot.

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1. Open Serial Console (e.g. putty)
   
   1. Speed: 115200
   2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
2. Linux Console:
   Note: Wait until Linux boot finished For Linux Login use:
   
   1. User Name: root
   2. Password: root
3. You can use Linux shell now.
   1. I2C 0 Bus type: i2cdetect -y -r 0
   2. ETH0 works with udhcpc
   3. USB type  "lsusb" or connect USB device
   4. PCIe type "lspci"

Vivado HW Manager

(coming soon)

System Design - Vivado

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PS Interfaces

Activated interfaces:

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Control:

• User LED Control (D16, D15)
  

Monitoring:

• MGT CLK Measurement:
  • Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz
  • Default B229_CLK1: 78,8MHz, B128_CLK1: 150MHz, B129_CLK1: 175MHz, B130_CLK1: 200MHz, B228_CLK1: 125MHz, B23ß_CLK1: 100MHz
    

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System Design - Vivado

Block Design

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PS Interfaces

Activated interfaces:

Constrains

Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

# GT Clocks
#B128-1
set_property PACKAGE_PIN N27

Constrains

Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

# GT Clocks
#B128-1
set_property PACKAGE_PIN N27 [get_ports {PL_MGT_CLK_clk_p[0]}]
#B129-1
set_property PACKAGE_PIN J27 [get_ports {PL_MGT_CLK_clk_p[1]}]
#B228-1
set_property PACKAGE_PIN J8  [get_ports {PL_MGT_CLK_clk_p[2]}]
#B130-1
set_property PACKAGE_PIN E27 [get_ports {PL_MGT_CLK_clk_p[3]}]
#B229-1
set_property PACKAGE_PIN E8  [get_ports {PL_MGT_CLK_clk_p[4]}]
#B230-1
set_property PACKAGE_PIN B10 [get_ports {PL_MGT_CLK_clk_p[50]}]

## DP#B129-1
set_property PACKAGE_PIN AB1J27 [get_ports dp_aux_data_in]
{PL_MGT_CLK_clk_p[1]}]
#B228-1
set_property PACKAGE_PIN J8 V9 [get_ports dp{PL_hotMGT_plug_detect]CLK_clk_p[2]}]
#B130-1
set_property PACKAGE_PIN AA8E27 [get_ports dp_aux_data_out]
{PL_MGT_CLK_clk_p[3]}]
#B229-1
set_property PACKAGE_PIN AA3E8  [get_ports dp{PL_auxMGT_dataCLK_oe_n]clk_p[4]}]
#B230-1
set_property IOSTANDARDPACKAGE_PIN LVCMOS18B10 [get_ports dp_*{PL_MGT_CLK_clk_p[5]}]

## LEDDP
set_property PACKAGE_PIN K14AB1 [get_ports {LED[0]}]
set_dp_aux_data_in]
set_property PACKAGE_PIN K10V9 [get_ports {LED[1]}]dp_hot_plug_detect]
set_property IOSTANDARDPACKAGE_PIN LVCMOS18AA8 [get_ports {LED*}]

Software Design - SDK/HSI

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For SDK project creation, follow instructions from:

SDK Projects

Application

SDK template in ./sw_lib/sw_apps/ available.

zynqmp_fsbl

TE modified 2018.2 FSBL

Changes:

• Si5345Configuration
  
  •  see xfsbl_board.c and xfsbl_board.h, xfsbl_main.c
  • Add Si5345-Registers.h, si5345.c, si5345.h, si5338.c, si5338.h, register_map.h

Note: Remove compiler flags "-Os -flto -ffat-lto-objects" on 2018.2 SDK to generate FSBL

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dp_aux_data_out]
set_property PACKAGE_PIN AA3  [get_ports dp_aux_data_oe_n]
set_property IOSTANDARD LVCMOS18 [get_ports dp_*]
## LED
set_property PACKAGE_PIN K14 [get_ports {LED[0]}]
set_property PACKAGE_PIN K10 [get_ports {LED[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {LED*}]

Software Design - SDK/HSI

For SDK project creation, follow instructions from:

SDK Projects

Application

SDK template in ./sw_lib/sw_apps/ available.

zynqmp_fsbl

TE modified 2018.2 FSBL

Changes:

• Set FSBL Boot Mode to JTAG
• Disable Memory initialisation

• Si5345Configuration
  
  •  see xfsbl_board.c and xfsbl_board.h, xfsbl_main.c
  • Add Si5345-Registers.h, si5345.c, si5345.h, si5338.c, si5338.h, register_map.h

Note: Note: Remove compiler flags "-Os -flto -ffat-lto-objects" on 2018.2 SDK to generate FSBL

zynqmp_

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fsbl_flash

TE modified 2018.2 FSBL

Changes:

• Set FSBL Boot Mode to JTAG
• Disable Memory initialisation

Note: Remove compiler flags "-Os -flto -ffat-lto-objects" on 2018.2 SDK to generate FSBL

zynqmp_pmufw

Xilinx default PMU firmware.

hello_teb0911

Hello TEB0911 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is

Xilinx default PMU firmware.

hello_teb0911

Hello TEB0911 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

For PetaLinux installation and  project creation, follow instructions from:

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/include/ "system-conf.dtsi"
/ {
};

/* USB  */

&dwc3_0 {
    status = "okay";
    dr_mode = "host";
};


/* QSPI */

&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};



/* ETH */

&gem3 {
        phy-handle = <&phy0>;
        phy0: phy0@1 {
                device_type = "ethernet-phy";
                reg = <1>;
        };
};



/* SD1 */

&sdhci1 {
    // disable-wp;
    no-1-8-v;

};


&i2c0 {
    i2cswitch@76 { // I2C Switch U13
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x76>;
        i2c-mux-idle-disconnect;

        i2c@2 { // FMCD (/dev/i2c-3)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <2>;
        };
        i2c@3 { // FMCE (/dev/i2c-4)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;
        };
        i2c@4 { // FMCB (/dev/i2c-5)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <4>;
        };
        i2c@5 { // FMCC (/dev/i2c-6)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <5>;
        };
        i2c@6 { // PLL (/dev/i2c-7)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <6>;

            si570_2: clock-generator3@5d {
                #clock-cells = <0>;
                compatible = "silabs,si570";
                reg = <0x5d>;
                temperature-stability = <50>;
                factory-fout = <156250000>;
                clock-frequency = <78800000>;

            };
        };
    };
    i2cswitch@77 { // I2C Switch U37
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x77>;
        i2c-mux-idle-disconnect;

        i2c@0 { // SFP2 (/dev/i2c-9)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0>;
        };
        i2c@1 { // FMCA (/dev/i2c-10)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>;
        };
        i2c@2 { // FMCF (/dev/i2c-11)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <2>;
        };
        i2c@3 { // SFP0 (/dev/i2c-12)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;
        };
        i2c@4 { // SFP1 (/dev/i2c-13)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <4>;
        };
        i2c@5 { // MEM (/dev/i2c-14)
            // Low frequency to work with CPLD
            clock-frequency = <100000>;
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <5>;
        };
        i2c@6 { // DDR4 (/dev/i2c-15)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <6>;
        };
        i2c@7 { // USBH (/dev/i2c-16)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <7>;
        };

    };
};

/* UNUSED DMA disable */

&lpd_dma_chan1 {
    status = "disabled";
};
&lpd_dma_chan2 {
    status = "disabled";
};
&lpd_dma_chan3 {
    status = "disabled";
};
&lpd_dma_chan4 {
    status = "disabled";
};
&lpd_dma_chan5 {
    status = "disabled";
};
&lpd_dma_chan6 {
    status = "disabled";
};
&lpd_dma_chan7 {
    status = "disabled";
};
&lpd_dma_chan8 {
    status = "disabled";
};

Kernel

Deactivate:

• CONFIG_CPU_IDLE      (only needed to fix JTAG Debug issue)

• CONFIG_CPU_FREQ    (only needed to fix JTAG Debug issue)

Rootfs

Activate:

• i2c-tools

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

Additional Software

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Add Description for other Software, for example SI CLK Builder ...
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No additional software is needed.

SI5338

Download  ClockBuilder Desktop for SI5338

1. Install and start ClockBuilder
2. Select SI5338
3. Options → Open register map file
   Note: File location <design name>/misc/Si5338/RegisterMap.txt
4. Modify settings
5. Options → save C code header files
6. Replace Header files from FSBL template with generated file

SI5345

Download  ClockBuilder Pro for SI5345

1. Install and start ClockBuilder
2. Open "/misc/SI5345/Si5345-RevB-0808-02A-Project.slabtimeproj"
3. Modify settings
4. Export → Register File → select C code header → save to file
5. Replace Header files from FSBL template with generated file

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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Kernel

Deactivate:

• CONFIG_CPU_IDLE      (only needed to fix JTAG Debug issue)

• CONFIG_CPU_FREQ    (only needed to fix JTAG Debug issue)

Rootfs

Activate:

• i2c-tools

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

Additional Software

No additional software is needed.

SI5338

File location <design name>/misc/Si5338/RegisterMap.txt

General documentation how you work with these project will be available on Si5338

SI5345

File location <design name>/misc/Si5345/Si5345-RevD-0911-Project.slabtimeproj

General documentation how you work with these project will be available on Si5345

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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• Initial release

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Legal Notices

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