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SC is connected directly to the following B2B Pins.
| Name | Mode | Default function | Alternative | Description |
|---|---|---|---|---|
| EN1 | input, weak pull-up | Power Enable | IO | High enables the DC-DC converters and on-board supplies. Not used if NOSEQ=1 |
| PGOOD | output, open drain | Power good | SCL or IO | Forced low until all on-board power supplies are working properly. Attention: During CPLD programming, this pins is high impedance |
| MODE | input, weak pull-up | Boot mode | SDA or IO | Force low for boot from the SD Card. Latched at power on only, not on soft reset! |
| RESIN | input, weak pull-up | Reset input | IO | Active Low Reset input, default mapping forces POR_B reset to Zynq PS |
| NOSEQ | input, weak pull-down | Power sequencing Control | Output | Forces the 1.0V and 1.8V DC-DC converters always ON when high. Can be used as an I/O after boot. |
| JTAGSEL | input | JTAG Chain select | none, fixed | keep GND or pulled low for FPGA JTAG access. |
NOSEQ Pin
This is a dedicated input that forces the module's 1.0V and 1.8V supplies to be enabled if high. This pin has a weak pull-down on the module. If left open the module will power up in normal power sequencing enabled mode. This pin is 3.3V tolerant. This pin is also connected to the System Management Controller. The SC can read the status of this pin (that is it can detect if the module is in power sequencing enabled mode). The SC can also use this pin as output after normal power on sequence. Please check the SC description for the function. SC rev 0.02 maps Ethernet PHY LED0 to NOSEQ by default (the mapping can be changed by software after boot).
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NOSEQ can be used as an output after boot. NOSEQ must be low when 3.3V power is applied to the module. Common usage is an LED connected between NOSEQ and GND.
SC pins to the FPGA
| Schematic net name | Default function | Direction | SC pin | FPGA pin | Description |
|---|---|---|---|---|---|
| XCLK | ETH PHY Clock to FPGA | to FPGA | K1 | K19 | |
| X1 | I2C Clock from FPGA | from FPGA | F1 | L16 | SCL from EMIO I2Cx |
| X7 | I2C Data from FPGA | from FPGA | M1 | N22 | SDA from EMIO I2Cx |
| X5 | I2C Data to FPGA | to FPGA | J1 | P22 | SDA to EMIO I2Cx |
| X2 | ETH PHY LED1 | to FPGA | C2 | M15 | |
| X4 | ETH PHY LED2 | to FPGA | D1 | P16 | |
| X3 | Interrupt | to FPGA | B1 | N15 | RTC, MEMS Interrupt or PHY LED3 |
| X0 | - | - | not used on TE0720-02 | ||
| PUDC | K16 | normally not used tied to fixed level by SC |
It is recommended to use Vivado IP Core available for 2014.2 and later versions.
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At power up the System Management Controller starts with default settings.
| Pin/Function | Used as/Mapped to | Notes |
|---|---|---|
| ETH PHY LED0 | XIO to FPGA | |
| ETH PHY LED1 | XIO to FPGA | |
| ETH PHY LED2 | Not used | |
| ETH PHY CONFIG | Tied logic low | PHY Address set to 0 |
| ETH CLK125MHz | Pass through FPGA B34 SRCC pin | |
| ETH Clock Enable | Tied logic high | |
| ETH PHY Reset | Internal RESET | |
| MIO7 | LED1 | |
| MEMS/RTC I2C | XIO to FPGA | |
| RTC Interrupt | - | |
| MEMS Interrupt 1 | - | |
| MEMS Interrupt 2 | - | |
| eMMC Reset | Internal RESET | |
| USB PHY Reset | Internal RESET | |
| FPGA PUDC | Tied logic low | |
| FPGA PROG_B | Tied logic high | |
| Zynq Cascaded JTAG | Enabled (pulled low) | |
| Zynq boot mode | SPI or SD, depending on bootmode pin | |
| Zynq SRST | Tied logic high | |
| Zynq POR | Internal POR/Reset | |
| PLL | Not used | |
| LED2 | System Status LED | |
| LED1 | MIO7 | |
| NOSEQ Input | NOSEQ at power, LED out after boot | |
| Power Good 1.5V | ||
| Power Good VTT | ||
| MODE Input |
| I2C Address | Function | |
|---|---|---|
| 0x20 | Status reg 1 | |
| 0x21 | Status reg 2 |
LED Control Status
The TE0720 on-board LED devices can be remapped to different functions.
| Input port bit | Mapped to |
|---|---|
| 0 | Ethernet PHY LED0 output |
| 1 | Ethernet PHY LED1 output |
| 2 | Ethernet PHY LED2 output |
| 3 | PS MIO7 |
| 4 | Returns RESIN pin level |
| 5 | Returns EN1 pin level |
| 6 | Returns NOSEQ pin level |
| 7 | Returns MODE pin level |
LED1 and LED2 function can be changed from the default behaviour using output port bits (3..0)
| D3 | D2 | D1 | D0 | LED1 function as |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | Default (MIO7) |
| 0 | 0 | 0 | 1 | ETH PHY LED0 |
| 0 | 0 | 1 | 0 | ETH PHY LED1 |
| 0 | 0 | 1 | 1 | ETH PHY LED2 |
| 0 | 1 | 0 | 0 | MIO7 |
| 0 | 1 | 0 | 1 | Undefined |
| 0 | 1 | 1 | 0 | OFF |
| 0 | 1 | 1 | 1 | ON |
| 1 | x | x | x | Undefined |
SC Demystified
System Controller (SC for short) was designed to allow ZYNQ PS system to access module special functions as early as possible without reducing the number of MIO pins that are fully user configurable.
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PHY at address 0x1A is the System Controller. OUI 0x7201 should be decoded as Model TE0720-01. Model 0x01 is Assembly option. Rev 0x00 is the firmware major revision for the System Controller (Rev 0 is the initial version).
Bit Decoding
| Reg Addr | Bits | u-boot ENV Variable | Description |
|---|---|---|---|
| 2 | 15:0 | board | upper bits of SoM Model |
| 3 | 15:10 | board | lower bits of SoM Model |
| 4 | 15:14 | board | FPGA Speed Grade (1, 2 or 3) |
| 4 | 13:12 | board | FPGA Temperature Range (0=Commercial, 1=Extended, 2=Industrial, 3=Automotive) |
| 4 | 11:8 | - | Assembly Variant |
| 4 | 7:0 | scver | SC Firmware Revision Minor number |
Customized u-boot reads and decodes the model and assembly variant information and stores in readable format in environment variables.
zynq-uboot> printenv board
board=TE0720-01-2IF
zynq-uboot>
Reading MAC Address
With u-boot command mii read:
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Customized u-boot does read MAC Address and stores it in environment variables as required, as a result, proper MAC address is used both in u-boot as also in Linux. Setting up MAC Address for Linux involves dynamic rewrite of FDT, this is done with u-boot script that starts Linux.
SC Registers
Most registers and functions are available via ETH PHY Management interface (MIO pins 52 and 53).
| Addr | R/W | Register name | Descripion |
|---|---|---|---|
| 0 | RO | ||
| 1 | RO | ||
| 2 | RO | ID1 | Identifier Register 1 |
| 3 | RO | ID2 | Identifier Register 2 |
| 4 | RO | ID3 | Identifier Register 3 |
| 5 | RW | CR1 | Control Register 1: LED's |
| 6 | RW | CR2 | Control Register 2; XIO Control |
| 7 | RW | CR3 | Control Register 3; Reset, Interrupt |
| 8 | RO | SR1 | Status Register |
| 9 | RO | MAChi | Highest bytes of primary MAC Address |
| 0xA | RO | MACmi | Middle bytes of primary MAC Address |
| 0xB | RO | MAClo | Lowest bytes of primary MAC Address |
| 0xC | CR4 | reserved do not use | |
| 0xD | RW | MMD_CR | MMD Control Register |
| 0xE | RW | MMD_AD | MMD Address/Data |
| 0xF | - | reserved do no use | |
| other | - | reserved do not use |
Register CR1
| Bit | Description |
|---|---|
| 15:12 | - |
| 11:8 | Noseq MUX |
| 7:4 | LED2 MUX |
| 3:0 | LED1 MUX |
| Value | LED1 | LED2 | NOSEQ | |
|---|---|---|---|---|
| Default | MIO7 | Mode Blink | PHY_LED0 | |
| 0001 | PHY_LED0 | PHY_LED0 | PHY_LED0 | |
| 0010 | PHY_LED1 | PHY_LED1 | PHY_LED1 | |
| 0011 | PHY_LED2 | PHY_LED2 | PHY_LED2 | |
| 0100 | MIO7 | MIO7 | MIO7 | |
| 0101 | RTC_INT | RTC_INT | RTC_INT | |
| 0110 | OFF | OFF | OFF | |
| 0111 | ON | ON | ON | |
| 1000 | MIO14/MIO15 | MIO14/MIO15 | REV 05, UART activity | |
| 1001 | MIO14 | MIO15 | REV 05 | |
| 1010 | REV 05 |
Register CR2
| Bit | Description |
|---|---|
| 15:12 | XCLK select |
| 11:8 | XIO6 select |
| 7:4 | XIO5 select |
| 3:0 | XIO4 select |
Signal XIO4
| XIO4 select | Signal out value |
|---|---|
| "0001" | MIO7 |
| "0010" | SHA_IO |
| "0011" | MAC_IO |
| "0110" | 'Z' (Configured as input) |
| all others | PHY_LED0 |
Signal XIO5
| XIO5 select | Signal out value |
|---|---|
| "0101" | RTC_INT |
| "0110" | 'Z' (Configured as input) |
| all others | PHY_LED1 |
Signal XIO6
| XIO6 select | Signal out value |
|---|---|
| "0110" | 'Z' (Configured as input) |
| "0111" | INTR |
| all others | PHY_LED2 |
Signal XCLK
| XCLK Select | Signal out value |
|---|---|
| "0001" | RTC_INT |
| "0010" | Internal Oscillator Out ~24.18 MHz |
| all others | 125 MHz |
Signal SHA_IO
| XIO4 select | Signal out value |
|---|---|
| "0010" | XIO5 |
| all others | 'Z' (Configured as input) |
Signal MAC_IO
| XIO4 Select | Signal out value |
|---|---|
| "0011" | XIO5 |
| all others | Connected to internal MAC read block |
System Controller version 0.02 does not support extended address space - registers 0xD and 0xE are read-write accessible but do not have any function. In feature revision extended address will be used to control SC PLL and other features.
| Bit | Description |
|---|---|
| 0 | enable INT1 |
| 1 | enable INT2 |
| 2 | enable RTC_INT |
| 3 | enable PHY_LED2 |
CR3 bit description
Interrupt can be selected instead of PHY_LED2 on XIO6 pin, by setting CR2 bits 11 downto 8 to "0111"
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