Page History

<!--
Template Revision 1.0
Basic Notes
 - export PDF to download, if vivado revision is changed!
 - Template is for different design and SDSoC and examples, remove unused or wrong description!
 -->

Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation

Overview

<!--
General Design description
 -->

Key Features

<!--
Add Basic Key Features of the design (should be tested)
 -->

Revision History

<!--
- Add changes from design
- Export PDF to download, if vivado revision is changed!
  -->

...

• chance block design: qspi clks, clock wizard(REV01 only)
• change timing constrains
• add hello_te0712 application
• new SREC bootloader version
• change linux device tree

...

• solved eth issue for REV01
• changed design + second design for REV01

...

• bugfix constrain file - ETH REFCLK, timing

...

• new assembly variant

...

• no design changes
• small constrain changes

...

• add SI5338 initialisation with MCS
• add Ethernet IP

...

• add wiki link in Boart Part Files
• set correct short link for te0712-02-200-2c

...

tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
.wrapped{
  width: 100% !important;
  max-width: 1200px !important;
 }
</style>

Overview

Microblaze Design with linux example.

Refer to http://trenz.org/te0720-info for the current online version of this manual and other available documentation.

Key Features

Revision History

...

...

...

...

...

...

• initial release

Release Notes and Know Issues

<!--
- add known Design issues and general Notes for the current revision
 -->

...

SREC SPI BootLoader default Offset

...

Release Notes and Know Issues

Requirements

Software

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Design supports following carriers:

Additional HW Requirements:

Content

For general structure and of the reference design, see Project Delivery

Design Sources

Additional Sources

Prebuilt

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

• TE0712 "Test Board" Reference Design

Design Flow

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:Vivado/SDK/SDSoC

• Vivado/SDK/SDSoC
• Vivado Projects
•  Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
   Image Added
2. Press 0 and enter to start "Module Selection Guide"
3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
   
   1. optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
5. Create HDF and export to prebuilt folder
   
   1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
6. Create Linux (uboot.elf and image.ub) with exported HDF
   
   1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
   2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
         Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
         Important Note: Select correct Flash partition offset on petalinux-config: Subsystem Auto HW Settings → Flash Settings,  FPGA+Boot+bootenv=0x900000 (increase automatically generate Boot partition), increas image size to A:, see 54395771
7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
   
   1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
8. (not longer needed manually: This will be done with Step 10.a automatically with newer scripts (2017.4.10) ) Generate UBoot SREC:
   1. Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_sdk
   2. Create "uboot-dummy" application
      Note: Use Hello World Example
   3. Copy u-boot.elf into "\workspace\sdk\uboot-dummy\Debug"
   4. Open "uboot-dummy" properties → C/C++ Build → Settings and go into Build Steps Tap.
   5. Add to Post-build steps: mb-objcopy -O srec u-boot.elf u-boot.srec
   6. Press Apply or regenerate project
      Note: SREC is generated on "\workspace\sdk\uboot-dummy\Debug\u-boot.srec"
9. Generate MCS Firmware (optional):
   1. Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_sdk
   2. Create "SCU" application
      Note: Select MCS Microblaze and SCU Application
   3. Select Release Built
   4. Regenerate App
10. Generate Programming Files with HSI/SDK
    
    1. Run on Vivado TCL: TE::sw_run_hsi
       Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
       Note: See SDK Projects
11. Copy "\prebuilt\software\<short name>\srec_spi_bootloader.elf" into  "\firmware\microblaze_0\"
12. (optional) Copy "\\workspace\sdk\scu\Release\scu.elf" into  "\firmware\microblaze_mcs_0\"
13. Regenerate Vivado Project or Update Bitfile only with "srec_spi_bootloader.elf" and "scu.elf"

Launch

Programming

<!--
Description of Block Design, Constrains...
BD Pictures from Export...
  -->

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

1. Connect JTAG and power on PCB
2. (if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
3. Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
   Note: Alternative use SDK or setup Flash on Vivado manually
             optional "TE::pr_program_flash_binfile -swapp hello_te0712" possible
4. Reboot (if not done automatically)

SD

Not used on this Example.

JTAG

Not used on this Example.

Usage

1. Prepare HW like described on section 54395771
2. Connect UART USB (most cases same as JTAG)
3. Power on PCB
   Note: FPGA Loads Bitfile from Flash,MCS Firmware configure SI5338 and starts Microblaze, SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), U-boot loads Linux from QSPI Flash into DDR

Boot process takes a while, please wait.

Image Added

Linux

Note: Linux boot process is slower on Microblaze.

1. Open Serial Console (e.g. putty)
   
   1. Speed: 9600
   2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
2. Linux Console:
   Note: Wait until Linux boot finished For Linux Login use:
   
   1. User Name: root
   2. Password: root
3. You can use Linux shell now.
   1. ETH0 works with udhcpc
      

Vivado HW Manager: 

• Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
  1. Set radix from VIO signals (MGT REF, MIG_OUT, CLK1B, CLK0) to unsigned integer.
     Note: Frequency Counter is inaccurate and displayed unit is Hz
• Monitoring:
  
  • MGT REF~125MHz, MIG_50MHZ~50MHz., CLK1B ~50MHz, CLK0~100MHz
  • System reset from MCS and GIO outputs

Scroll Title
anchor Figure_VHM title Vivado Hardware Manager
Image Added

System Design - Vivado

Block Design

Scroll Title
anchor Figure_BD title Block Design PCB REV02
Image Added

REV01

Scroll Title
anchor Figure_BD title Block Design PCB REV01 (Same as REV02 but 50 MHz ETH REV CLK is generated from MIG output with 180° Phase shift.)
Image Added

Constrains

Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Requirements

Software

<!--
Add needed external Software
   -->

...

Hardware

<!--
Hardware Support
   -->

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

...

01_100_2c

...

100_2c

...

100_2ca

...

te0712-02-200-1i3

...

200_1i

...

Design supports following carriers:

...

Additional HW Requirements:

...

Content

<!--
Remove unused content
  -->

For general structure and of the reference design, see Project Delivery

Design Sources

...

Additional Sources

...

Prebuilt

<!-- 

<table width="100%">
<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
</table>
-->

...

File

...

File-Extension

...

Description

...

MCS-File

...

*.mcs

...

Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

...

MMI-File

...

*.mmi

...

File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

...

SREC-File

...

*.srec

...

Converted Software Application for MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

<!--
Add correct path:https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0803/Reference_Design/2017.1/Starterkit
  -->

Reference Design is available on:

• TE0712 "Test Board" Reference Design

Design Flow

<!--
Basic Design Steps
Add/ Remove project specific 
  -->

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:Vivado/SDK/SDSoC

• Vivado/SDK/SDSoC
• Vivado Projects
•  Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
   Image Removed
2. Press 0 and enter for minimum setup
3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
4. Create Project
   
   1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
5. Create HDF and export to prebuilt folder
   
   1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
6. Create Linux (uboot.elf and image.ub) with exported HDF
   
   1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
   2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
         Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
         Important Note: Select correct Flash partition offset on petalinux-config: Subsystem Auto HW Settings → Flash Settings,  FPGA+Boot+bootenv=0x900000 (increase automatically generate Boot partition), increas image size to A:, see Config
7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
   
   1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
8. (not longer needed manually: This will be done with Step 10.a automatically with newer scripts (2017.4.10) ) Generate UBoot SREC:
   1. Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_sdk
   2. Create "uboot-dummy" application
      Note: Use Hello World Example
   3. Copy u-boot.elf into "\workspace\sdk\uboot-dummy\Debug"
   4. Open "uboot-dummy" properties → C/C++ Build → Settings and go into Build Steps Tap.
   5. Add to Post-build steps: mb-objcopy -O srec u-boot.elf u-boot.srec
   6. Press Apply or regenerate project
      Note: SREC is generated on "\workspace\sdk\uboot-dummy\Debug\u-boot.srec"
9. Generate MCS Firmware (optional):
   1. Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_sdk
   2. Create "SCU" application
      Note: Select MCS Microblaze and SCU Application
   3. Select Release Built
   4. Regenerate App
10. Generate Programming Files with HSI/SDK
    
    1. Run on Vivado TCL: TE::sw_run_hsi
       Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
       Note: See SDK Projects
11. Copy "\prebuilt\software\<short name>\srec_spi_bootloader.elf" into  "\firmware\microblaze_0\"
12. (optional) Copy "\\workspace\sdk\scu\Release\scu.elf" into  "\firmware\microblaze_mcs_0\"
13. Regenerate Vivado Project or Update Bitfile only with "srec_spi_bootloader.elf" and "scu.elf"

Launch

Programming

<!--
Description of Block Design, Constrains...
BD Pictures from Export...
  -->

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

1. Connect JTAG and power on PCB
2. (if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
3. Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
   Note: Alternative use SDK or setup Flash on Vivado manually
             optional "TE::pr_program_flash_binfile -swapp hello_te0712" possible
4. Reboot (if not done automatically)

SD

Not used on this Example.

JTAG

Not used on this Example.

Usage

1. Prepare HW like described on section Programming
2. Connect UART USB (most cases same as JTAG)
3. Power on PCB
   Note: FPGA Loads Bitfile from Flash,MCS Firmware configure SI5338 and starts Microblaze, SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), U-boot loads Linux from QSPI Flash into DDR

Boot process takes a while, please wait.

Image Removed

Linux

Note: Linux boot process is slower on Microblaze.

1. Open Serial Console (e.g. putty)
   
   1. Speed: 9600
   2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
2. Linux Console:
   Note: Wait until Linux boot finished For Linux Login use:
   
   1. User Name: root
   2. Password: root
3. You can use Linux shell now.
   1. ETH0 works with udhcpc
      

Vivado HW Manager: 

1. Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
   1. Set radix from VIO signals (MGT REF, MIG_OUT, CLK1B, CLK0) to unsigned integer.
      Note: Frequency Counter is inaccurate and displayed unit is Hz
   2. MGT REF~125MHz, MIG_50MHZ~50MHz., CLK1B ~50MHz, CLK0~100MHz
   3. Additional Infos: System reset from MCS and GIO outputs
      

Image Removed

System Design - Vivado

<!--
Description of Block Design, Constrains...
BD Pictures from Export...
  -->

Block Design

REV02

Image Removed

REV01

Same as REV02 but 50 MHz ETH REV CLK is generated from MIG output with 180° Phase shift.

Image Removed

Constrains

Basic module constrains

set_property BITSTREAM.GENERALCONFIG.COMPRESSUNUSEDPIN TRUEPULLDOWN [current_design]

Design specific constrain

set_property BITSTREAM.CONFIG.CONFIGRATE 66PULLDOWN true [currentget_design]
setports reset]

#I2C
#set_property CONFIGPACKAGE_VOLTAGEPIN 3.3W21 [current_designget_ports PLL_I2C_scl_io]
set#set_property CFGBVSIOSTANDARD VCCOLVCMOS33 [current_designget_ports PLL_I2C_scl_io]
set#set_property CONFIGPACKAGE_MODEPIN SPIx4T20 [current_designget_ports PLL_I2C_sda_io]
set#set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_designIOSTANDARD LVCMOS33 [get_ports PLL_I2C_sda_io]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_designPACKAGE_PIN W21 [get_ports PLL_I2C_ext_scl_o]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_designIOSTANDARD LVCMOS33 [get_ports PLL_I2C_ext_scl_o]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_designPACKAGE_PIN T20 [get_ports PLL_I2C_ext_sda]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]
IOSTANDARD LVCMOS33 [get_ports PLL_I2C_ext_sda]

#Reset
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMPPACKAGE_PIN T3 [currentget_design]

ports reset]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWNIOSTANDARD LVCMOS15 [current_design]

Design specific constrain

get_ports reset]
#CLKS
set_property PULLDOWNPACKAGE_PIN trueR4 [get_ports reset]

#I2C
#set{CLK1B[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {CLK1B[0]}]
set_property PACKAGE_PIN W21K4 [get_ports PLL{CLK0_I2C_scl_ioclk_p[0]}]
#setset_property IOSTANDARD LVCMOS33DIFF_SSTL15 [get_ports PLL_I2C_scl_io]
#set{CLK0_clk_p[0]}]

#ETH PHY
set_property PACKAGE_PIN T20N17 [get_ports PLLphy_I2Crst_sda_ion]
#setset_property IOSTANDARD LVCMOS33 [get_ports PLL_I2C_sda_io]
set_property PACKAGE_PIN W21phy_rst_n

create_clock -period 8.000 -name mgt_clk0_clk_p -waveform {0.000 4.000} [get_ports PLLmgt_I2Cclk0_extclk_scl_o]
set_property IOSTANDARD LVCMOS33p]


create_clock -period 10.000 -name {CLK0_clk_p[0]} -waveform {0.000 5.000} [get_ports PLL{CLK0_I2C_ext_scl_oclk_p[0]}]
set_property PACKAGE_PIN T20create_clock -period 20.000 -name {CLK1B[0]} -waveform {0.000 10.000} [get_ports PLL_I2C_ext_sda{CLK1B[0]}]
set_property IOSTANDARD LVCMOS33create_clock -period 15.152 -name CFGMCLK -waveform {0.000 7.576} [get_ports PLL_I2C_ext_sda]

#Reset
set_property PACKAGE_PIN T3pins -hierarchical -filter {NAME =~*NO_DUAL_QUAD_MODE.QSPI_NORMAL/*STARTUP_7SERIES_GEN.STARTUP2_7SERIES_inst/CFGMCLK}]


set_false_path -from [get_ports reset]
set_property IOSTANDARD LVCMOS15 clocks {CLK0_clk_p[0]}] -to [get_ports resetclocks clk_pll_i]
#CLKS
set_property PACKAGEfalse_PINpath R4-from [get_ports {CLK1B[0]}]
set_property IOSTANDARD LVCMOS15 clocks mgt_clk0_clk_p] -to [get_ports {CLK1B[0]}clocks clk_pll_i]
set_property PACKAGEfalse_PINpath K4-from [get_portspins {CLK0_clk_p[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {CLK0_clk_p[0]}]

#ETH PHY
set_property PACKAGE_PIN N17 [get_ports phy_rst_n]
set_property IOSTANDARD LVCMOS33 [get_ports phy_rst_n

create_clock -period 8.000 -name mgt_clk0_clk_p -waveform {0.000 4.000} [get_portsmsys_i/SC0712_0/U0/rst_delay_i_reg[3]/C}] -to [get_pins -hierarchical -filter {NAME =~*u_msys_mig_7series_0_0_mig/u_ddr3_infrastructure/rstdiv0*/PRE}]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/mig_7series_0/u_msys_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT]] -to [get_clocks mgt_clk0_clk_p]


create_clockset_false_path -period 10.000 -name {CLK0_clk_p[0]} -waveform {0.000 5.000} [get_ports {CLK0_clk_pfrom [get_clocks clk_pll_i] -to [get_clocks {msys_i/util_ds_buf_0/U0/IBUF_OUT[0]}]
createset_false_clockpath -period 20.000 -name {CLK1B[0]} -waveform {0.000 10.000} [get_ports {CLK1B[0]}]
create_clock -period 15.152 -name CFGMCLK -waveform {0.000 7.576} [get_pins -hierarchical -filter {NAME =~*NO_DUAL_QUAD_MODE.QSPI_NORMAL/*STARTUP_7SERIES_GEN.STARTUP2_7SERIES_inst/CFGMCLK}]


set_false_path -from [get_clocks {CLK0_clk_p[0]}] -to [get_clocks clk_pll_ifrom [get_pins {msys_i/labtools_fmeter_0/U0/F_reg[*]/C}] -to [get_pins {msys_i/vio_0/inst/PROBE_IN_INST/probe_in_reg_reg[*]/D}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/COUNTER_REFCLK_inst/bl.DSP48E_2/CLK] -to [get_pins {msys_i/vio_0/inst/PROBE_IN_INST/probe_in_reg_reg[*]/D}]
set_false_path -from [get_clocks mgt_clk0_clk_p] -to [get_clocks clk_pll_i]
set_false_path -frompins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CLK}] -to [get_pins {msys_i/SC0712_0/U0/rst_delay_i_reg[3]/C}] -to [get_pins -hierarchical -filter {NAME =~*u_msys_mig_7series_0_0_mig/u_ddr3_infrastructure/rstdiv0*/PRE}]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/mig_7series_0/u_msys_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT]] -to [get_clocks mgt_clk0_clk_p]
set_false_path -from [get_clocks clk_pll_i] -to [get_clocks {msys_i/util_ds_buf_0/U0/IBUF_OUT[0]}]
set_false_path -from [get_pins {msys_i/labtools_fmeter_0/U0/F_reg[*]/C}] -to [get_pins {msys_i/vio_0/inst/PROBE_IN_INST/probe_in_reg_reg[*]/D}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/COUNTER_REFCLK_inst/bl.DSP48E_2/CLK] -to [get_pins {msys_i/vio_0/inst/PROBE_IN_INST/probe_in_reg_reg[*]/D}]
set_false_path -from [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CLK}] -to [get_pins {msys_i/labtools_fmeter_0/U0/F_reg[*]/D}]

Software Design - SDK/HSI

<!--
optional chapter
separate sections for different apps
  -->

For SDK project creation, follow instructions from:

SDK Projects

Application

Template location: ./sw_lib/sw_apps/

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

Boadloader to load app or second bootloader from flash into DDR

Changes:

• Add some vonsole outputs and changed bootloader read address.
• Add bugfix for 2018.2 qspi flash

xilisf_v5_11

• Changed default Flash Typ to 5.

hello_te0712

Hello TE0712 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate u-boot.srec. Vivado to generate *.mcs

Software Design -  PetaLinux

<!--
optional chapter
  -->

• PetaLinux KICKstart

Description currently not available.

Config

• Set kernel flash Address to 0x900000 and Kernel size to 0xA00000:
  (--> Subsystem Auto Hardware Settings --> Flash Settings)
  
  • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART0_SIZE = 0x5E0000
  • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART1_SIZE = 0x300000
  • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART2_SIZE =   0x20000
  • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART3_SIZE = 0xA00000

U-Boot

#include <configs/platform-auto.h>

#define CONFIG_SYS_BOOTM_LEN 0xF000000

/* ethernet - axi_ethernetlite_0 */
#undef CONFIG_PHY_XILINX
#undef XILINX_EMACLITE_BASEADDR    0x40E00000
#undef CONFIG_MII
#undef CONFIG_NET_MULTI
#undef CONFIG_NETCONSOLE    1
#undef CONFIG_SERVERIP    192.168.150.127
#undef CONFIG_IPADDR

/* PREBOOT */
#define CONFIG_PREBOOT    "echo U-BOOT for petalinux;setenv preboot; echo;"

Device Tree

labtools_fmeter_0/U0/F_reg[*]/D}]

Software Design - SDK/HSI

For SDK project creation, follow instructions from:

SDK Projects

Application

Template location: ./sw_lib/sw_apps/

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2018.3 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

• Modified Files: blconfig.h, bootloader.c
• Changes:
  
  • Add some console outputs and changed bootloader read address.
  • Add bugfix for 2018.2 qspi flash (some reinitialisation)

xilisf_v5_11

TE modified 2018.3 xilisf_v5_11

• Changed default Flash type to 5.

hello_te0712

Hello TE0712 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate u-boot.srec. Vivado to generate *.mcs

Software Design -  PetaLinux

• PetaLinux KICKstart

Description currently not available.

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

• SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART0_SIZE = 0x5E0000  
• SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART1_SIZE = 0x300000
• SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART2_SIZE =   0x20000
• SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART3_SIZE = 0xA00000
  
  • (Set kernel flash Address to 0x900000 and Kernel size to 0xA00000)

U-Boot

Start with petalinux-config -c u-boot

Changes:

• CONFIG_ENV_IS_NOWHERE=y

• # CONFIG_ENV_IS_IN_SPI_FLASH is not set

• # CONFIG_NETCONSOLE is not set

• # CONFIG_NET_TFTP_VARS is not set

• # CONFIG_PHY_ATHEROS is not set

• # CONFIG_PHY_BROADCOM is not set

• # CONFIG_PHY_DAVICOM is not set

• # CONFIG_PHY_LXT is not set

• # CONFIG_PHY_MARVELL is not set

• # CONFIG_PHY_MICREL is not set

• # CONFIG_PHY_NATSEMI is not set

• # CONFIG_PHY_REALTEK is not set

• CONFIG_PHY_TI=y

• CONFIG_PHY_XILINX=y

• # CONFIG_DM_ETH is not set

• # CONFIG_NETDEVICES is not set

Change platform-top.h:

#include <configs/platform-auto.h>

#define CONFIG_SYS_BOOTM_LEN 0xF000000

Device Tree

/include/ "system-conf.dtsi"
/ {
};

/* QSPI PHY */

&axi_quad_spi_0 {
    #address-cells = <1>;
    #size-cells = <0>;
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        spi-tx-bus-width=<1>;
        spi-rx-bus-width=<4>;
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
        spi-max-frequency = <25000000>;
    };
};


/* ETH PHY */
&axi_ethernetlite_0 {
    phy-handle = <&phy0>;
    mdio 

/include/ "system-conf.dtsi"
/ {
};

/* QSPI PHY */

&axi_quad_spi_0 {
    #address-cells = <1>;
    #size-cells = <0>;
    flash0: flash@0 {
        compatible#address-cells = "jedec,spi-nor"<1>;
        spi-tx-bus-width=<1>#size-cells = <0>;
         spi-rx-bus-width=<4>;
phy0: phy@0 {
            regdevice_type = <0x0>"ethernet-phy";
        #address-cells    reg = <1>;
        #size-cells = <1>;
        spi-max-frequency = <25000000>;
    };
};


/* ETH PHY */
&axi_ethernetlite_0 {
    phy-handle = <&phy0>;
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy0: phy@0 {
            device_type = "ethernet-phy";
            reg = <1>;
        };
    };
};

Kernel

No changes.

Rootfs

No changes.

Applications

No changes.

Additional Software

<!--
Add Description for other Software, for example SI CLK Builder ...
 -->

SI5338

Download  ClockBuilder Desktop for SI5338

1. Install and start ClockBuilder
2. Select SI5338
3. Options → Open register map file
   Note: File location <design name>/misc/Si5338/RegisterMap.txt
4. Modify settings
5. Options → save C code header files
6. Replace Header files from FSBL template with generated file

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

 };
    };
};

Kernel

Start with petalinux-config -c kernel

Changes:

• No changes.

Rootfs

Start with petalinux-config -c rootfs

Changes:

• No changes.

Applications

No additional application.

Additional Software

SI5338

File location <design name>/misc/Si5338/Si5338-*.slabtimeproj

General documentation how you work with these project will be available on Si5338

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

...

...

...

...

...

...

Legal Notices

...