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Template Revision 2.4 - on construction

Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"


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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation
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Table of contents

Table of Contents
outlinetrue

Overview

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General Design description
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Key Features

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Excerpt
  • PetaLinux
  • MicroBlaze
  • SREC
  • I2C
  • Flash
  • MIG
  • FMeter
  • SI5338 initialisation with MCS
  • ETH

Revision History

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...

  • chance block design: qspi clks, clock wizard(REV01 only)
  • change timing constrains
  • add hello_te0712 application
  • new SREC bootloader version
  • change linux device tree

...

  • solved eth issue for REV01
  • changed design + second design for REV01

...

  • bugfix constrain file - ETH REFCLK, timing

...

  • new assembly variant

...

  • no design changes
  • small constrain changes

...

  • add SI5338 initialisation with MCS
  • add Ethernet IP

...

  • add wiki link in Boart Part Files
  • set correct short link for te0712-02-200-2c

...

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Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template (note: inner scroll ignore/only only with drawIO object):

        Scroll Title
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        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)

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Table of contents

Table of Contents
outlinetrue

Overview

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Notes :


Microblaze Design with linux example.

Refer to http://trenz.org/te0720-info for the current online version of this manual and other available documentation.

Key Features

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Notes :

  • Add basic key futures, which can be tested with the design



Excerpt
  • Vivado 2018.3
  • PetaLinux
  • MicroBlaze
  • SREC
  • I2C
  • Flash
  • MIG
  • FMeter
  • SI5338 initialisation with MCS
  • ETH

Revision History

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Notes :

  • add every update file on the download
  • add design changes on description



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DateVivadoProject BuiltAuthorsDescription
2019-222018.3TE0712-test_board_noprebuilt-vivado_2018.3-build_01_20190222073819.zip
TE0712-test_board-vivado_2018.3-build_01_20190222073754.zip
John Hartfiel
  • TE Script update
  • linux changes
  • SCU rework
  • SI5338 CLKBuilder Pro Project
2018-09-052018.2te0712-test_board-vivado_

...

2018.2-build_03_

...

20180906071356.zip
te0712-test_board_noprebuilt-vivado_

...

2018.2-build_03_

...

Requirements

Software

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Hardware

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Hardware Support
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Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

...

01_100_2c

...

100_2c

...

100_2ca

...

te0712-02-200-1i3

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200_1i

...

Design supports following carriers:

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Additional HW Requirements:

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Content

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For general structure and of the reference design, see Project Delivery

Design Sources

...

Additional Sources

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Prebuilt

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<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
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File

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File-Extension

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Description

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MCS-File

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*.mcs

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Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

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MMI-File

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*.mmi

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File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

...

SREC-File

...

*.srec

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Converted Software Application for MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

Design Flow

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Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:Vivado/SDK/SDSoC

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
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  2. Press 0 and enter for minimum setup
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project
    1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (uboot.elf and image.ub) with exported HDF
    1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
        Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
        Important Note: Select correct Flash partition offset on petalinux-config: Subsystem Auto HW Settings → Flash Settings,  FPGA+Boot+bootenv=0x900000 (increase automatically generate Boot partition), increas image size to A:, see Config
  7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
  8. (not longer needed manually: This will be done with Step 10.a automatically with newer scripts (2017.4.10) ) Generate UBoot SREC:
    1. Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_sdk
    2. Create "uboot-dummy" application
      Note: Use Hello World Example
    3. Copy u-boot.elf into "\workspace\sdk\uboot-dummy\Debug"
    4. Open "uboot-dummy" properties → C/C++ Build → Settings and go into Build Steps Tap.
    5. Add to Post-build steps: mb-objcopy -O srec u-boot.elf u-boot.srec
    6. Press Apply or regenerate project
      Note: SREC is generated on "\workspace\sdk\uboot-dummy\Debug\u-boot.srec"
  9. Generate MCS Firmware (optional):
    1. Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_sdk
    2. Create "SCU" application
      Note: Select MCS Microblaze and SCU Application
    3. Select Release Built
    4. Regenerate App
  10. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects
  11. Copy "\prebuilt\software\<short name>\srec_spi_bootloader.elf" into  "\firmware\microblaze_0\"
  12. (optional) Copy "\\workspace\sdk\scu\Release\scu.elf" into  "\firmware\microblaze_mcs_0\"
  13. Regenerate Vivado Project or Update Bitfile only with "srec_spi_bootloader.elf" and "scu.elf"

Launch

Programming

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Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

  1. Connect JTAG and power on PCB
  2. (if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
  3. Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
    Note: Alternative use SDK or setup Flash on Vivado manually
              optional "TE::pr_program_flash_binfile -swapp hello_te0712" possible
  4. Reboot (if not done automatically)

SD

Not used on this Example.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Power on PCB
    Note: FPGA Loads Bitfile from Flash,MCS Firmware configure SI5338 and starts Microblaze, SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), U-boot loads Linux from QSPI Flash into DDR

Boot process takes a while, please wait.

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Linux

Note: Linux boot process is slower on Microblaze.

  1. Open Serial Console (e.g. putty)
    1. Speed: 9600
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
  3. You can use Linux shell now.
    1. ETH0 works with udhcpc

Vivado HW Manager: 

  1. Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
    1. Set radix from VIO signals (MGT REF, MIG_OUT, CLK1B, CLK0) to unsigned integer.
      Note: Frequency Counter is inaccurate and displayed unit is Hz
    2. MGT REF~125MHz, MIG_50MHZ~50MHz., CLK1B ~50MHz, CLK0~100MHz
    3. Additional Infos: System reset from MCS and GIO outputs

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System Design - Vivado

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Block Design

REV02

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REV01

Same as REV02 but 50 MHz ETH REV CLK is generated from MIG output with 180° Phase shift.

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Constrains

Basic module constrains

20180906071434.zipJohn Hartfiel

...

  • initial release

Release Notes and Know Issues

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SREC SPI BootLoader default Offset

...

  • chance block design: qspi clks, clock wizard(REV01 only)
  • change timing constrains
  • add hello_te0712 application
  • new SREC bootloader version
  • change linux device tree
2018-05-252017.4te0712-test_board-vivado_2017.4-build_10_20180525155402.zip
te0712-test_board_noprebuilt-vivado_2017.4-build_10_20180525155555.zip
John Hartfiel
  • solved eth issue for REV01
  • changed design + second design for REV01
2018-04-122017.4te0712-test_board-vivado_2017.4-build_07_20180412081225.zip
te0712-test_board_noprebuilt-vivado_2017.4-build_07_20180412081253.zip
John Hartfiel
  • bugfix constrain file - ETH REFCLK, timing
2018-03-282017.4te0712-test_board-vivado_2017.4-build_07_20180328145151.zip
te0712-test_board_noprebuilt-vivado_2017.4-build_07_20180328145135.zip
John Hartfiel
  • new assembly variant
2018-01-082017.4te0712-test_board-vivado_2017.4-build_02_20180108155712.zip
te0712-test_board_noprebuilt-vivado_2017.4-build_02_20180108155735.zip
John Hartfiel
  • no design changes
  • small constrain changes
2017-12-152017.2te0712-test_board-vivado_2017.2-build_07_20171215172447.zip
te0712-test_board_noprebuilt-vivado_2017.2-build_07_20171215172514.zip
John Hartfiel
  • add SI5338 initialisation with MCS
  • add Ethernet IP
2017-11-072017.2te0712-test_board-vivado_2017.2-build_05_20171107172917.zip
te0712-test_board_noprebuilt-vivado_2017.2-build_05_20171107172939.zip
John Hartfiel
  • add wiki link in Boart Part Files
  • set correct short link for te0712-02-200-2c
2017-10-052017.2te0712-test_board-vivado_2017.2-build_03_20171005082148.zip
te0712-test_board_noprebuilt-vivado_2017.2-build_03_20171005082225.zip
John Hartfiel
  • initial release


Release Notes and Know Issues

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Notes :
  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if  issue fixed



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IssuesDescriptionWorkaroundTo be fixed version
For PCB REV01 only:  prebuilt does not bootThere is a Pullup missing on REV01 I2C SCL, so SI5338 configuration over MCS failsRemove MCSsolved with 20180528 update
For PCB REV01 only: CLK1B is not available onadditional clk is not connected on PCBuse other internal generated CLK, maybe more effort is needed to get ETH runningsolved with 20180528 update

SREC SPI BootLoader default Offset

Default load offset is set to 0x400000Change manually on SDK to 0x5E0000solved with 20180412 update


Requirements

Software

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Notes :

  • list of software which was used to generate the design



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SoftwareVersionNote
Vivado2018.3needed
SDK2018.3needed
PetaLinux2018.3needed
SI ClockBuilder Pro---optional


Hardware

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Notes :

  • list of software which was used to generate the design



Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

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Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
 TE0712-01-100-1I  01_100_1i_1gb   REV01    1GB      32MBNA        NA                         NA    
 TE0712-01-100-2C  01_100_2c_1gb   REV01    1GB      32MBNA        NA                         NA    
 TE0712-01-100-2C3 01_100_2c_1gb   REV01    1GB      32MBNA        2.5 mm Samtec connectors NA    
 TE0712-01-200-1I  01_200_1i_1gb   REV01    1GB      32MBNA        NA                         NA    
 TE0712-01-200-2I  01_200_2i_1gb   REV01    1GB      32MBNA        NA                         NA    
 TE0712-01-200-2C  01_200_2c_1gb   REV01    1GB      32MBNA        NA                         NA    
 TE0712-01-200-2C3 01_200_2c_1gb   REV01    1GB      32MBNA        2.5 mm Samtec connectors NA    
 TE0712-02-35-2I   35_2i_1gb       REV02    1GB      32MBNA        NA                         NA    
 TE0712-02-100-1I  100_1i_1gb      REV02    1GB      32MBNA        NA                         NA    
 TE0712-02-100-2C  100_2c_1gb      REV02    1GB      32MBNA        NA                         NA    
 TE0712-02-100-2C3 100_2c_1gb      REV02    1GB      32MBNA        2.5 mm Samtec connectors NA    
 TE0712-02-200-1I  200_1i_1gb      REV02    1GB      32MBNA        NA                         NA    
 TE0712-02-200-1I3 200_1i_1gb      REV02    1GB      32MBNA        2.5 mm Samtec connectors NA    
 TE0712-02-200-2I  200_2i_1gb      REV02    1GB      32MBNA        NA                         NA    
 TE0712-02-200-2C  200_2c_1gb      REV02    1GB      32MBNA        NA                         NA    
 TE0712-02-200-2C3 200_2c_1gb      REV02    1GB      32MBNA        2.5 mm Samtec connectors NA    
 TE0712-02-100-2CA 100_2ca_1gb     REV02    1GB      32MBNA        NA                         Micron QSPI Flash


Design supports following carriers:

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Carrier ModelNotes
TE0701
TE0703 used as reference carrier
TE0705
TE0706
TEBA0841



Additional HW Requirements:

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Additional HardwareNotes
USB Cable for JTAG/UARTCheck Carrier Board and Programmer for correct typ
XMOD ProgrammerCarrier Board dependent, only if carrier has no own FTDI



Content

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  • content of the zip file

For general structure and of the reference design, see Project Delivery

Design Sources

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TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration


Additional Sources

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TypeLocationNotes
SI5338<design name>/misc/Si5338SI5338 Project with current PLL Configuration


Prebuilt

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  • prebuilt files
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      File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems




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File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIT-File*.bitFPGA (PL Part) Configuration File
DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File

MCS-File

*.mcs

Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

MMI-File

*.mmi

File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

SREC-File

*.srec

Converted Software Application for MicroBlaze Processor Systems


Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

Design Flow

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Notes :
  • Basic Design Steps

  • Add/ Remove project specific description



Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:Vivado/SDK/SDSoC

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality


  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
    Image Added
  2. Press 0 and enter to start "Module Selection Guide"
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
    1. optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (uboot.elf and image.ub) with exported HDF
    1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
        Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
        Important Note: Select correct Flash partition offset on petalinux-config: Subsystem Auto HW Settings → Flash Settings,  FPGA+Boot+bootenv=0x900000 (increase automatically generate Boot partition), increas image size to A:, see 54395771
  7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
  8. (not longer needed manually: This will be done with Step 10.a automatically with newer scripts (2017.4.10) ) Generate UBoot SREC:
    1. Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_sdk
    2. Create "uboot-dummy" application
      Note: Use Hello World Example
    3. Copy u-boot.elf into "\workspace\sdk\uboot-dummy\Debug"
    4. Open "uboot-dummy" properties → C/C++ Build → Settings and go into Build Steps Tap.
    5. Add to Post-build steps: mb-objcopy -O srec u-boot.elf u-boot.srec
    6. Press Apply or regenerate project
      Note: SREC is generated on "\workspace\sdk\uboot-dummy\Debug\u-boot.srec"
  9. Generate MCS Firmware (optional):
    1. Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_sdk
    2. Create "SCU" application
      Note: Select MCS Microblaze and SCU Application
    3. Select Release Built
    4. Regenerate App
  10. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects
  11. Copy "\prebuilt\software\<short name>\srec_spi_bootloader.elf" into  "\firmware\microblaze_0\"
  12. (optional) Copy "\\workspace\sdk\scu\Release\scu.elf" into  "\firmware\microblaze_mcs_0\"
  13. Regenerate Vivado Project or Update Bitfile only with "srec_spi_bootloader.elf" and "scu.elf"

Launch

Programming

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Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

  1. Connect JTAG and power on PCB
  2. (if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
  3. Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
    Note: Alternative use SDK or setup Flash on Vivado manually
              optional "TE::pr_program_flash_binfile -swapp hello_te0712" possible
  4. Reboot (if not done automatically)

SD

Not used on this Example.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section 54395771
  2. Connect UART USB (most cases same as JTAG)
  3. Power on PCB
    Note: FPGA Loads Bitfile from Flash,MCS Firmware configure SI5338 and starts Microblaze, SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), U-boot loads Linux from QSPI Flash into DDR

Boot process takes a while, please wait.

Image Added

Linux

Note: Linux boot process is slower on Microblaze.

  1. Open Serial Console (e.g. putty)
    1. Speed: 9600
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
  3. You can use Linux shell now.
    1. ETH0 works with udhcpc

Vivado HW Manager: 

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  • add notes for the signal either groups or topics, for example:

    Control:

    • add controllable IOs with short notes..

    Monitoring:

    • add short notes for signals which will be monitored only

    SI5338_CLK0 Counter: 

    Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz


  • Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
    1. Set radix from VIO signals (MGT REF, MIG_OUT, CLK1B, CLK0) to unsigned integer.
      Note: Frequency Counter is inaccurate and displayed unit is Hz
  • Monitoring:
    • MGT REF~125MHz, MIG_50MHZ~50MHz., CLK1B ~50MHz, CLK0~100MHz
    • System reset from MCS and GIO outputs
Scroll Title
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titleVivado Hardware Manager
Image Added

System Design - Vivado

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Block Design

Scroll Title
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titleBlock Design PCB REV02
Image Added


REV01

Scroll Title
anchorFigure_BD
titleBlock Design PCB REV01 (Same as REV02 but 50 MHz ETH REV CLK is generated from MIG output with 180° Phase shift.)
Image Added


Constrains

Basic module constrains

Code Block
languageruby
title_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]


Code Block
languageruby
title_i_bitgen_common.xdc
set_property BITSTREAM.GENERALCONFIG.COMPRESSUNUSEDPIN TRUEPULLDOWN [current_design]

Design specific constrain

Code Block
languageruby
title_i_reset.xdc
linenumberstrue
set_property BITSTREAM.CONFIG.CONFIGRATE 66PULLDOWN true [currentget_design]
setports reset]


Code Block
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title_i_io.xdc
linenumberstrue
#I2C
#set_property CONFIGPACKAGE_VOLTAGEPIN 3.3W21 [current_designget_ports PLL_I2C_scl_io]
set#set_property CFGBVSIOSTANDARD VCCOLVCMOS33 [current_designget_ports PLL_I2C_scl_io]
set#set_property CONFIGPACKAGE_MODEPIN SPIx4T20 [current_designget_ports PLL_I2C_sda_io]
set#set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_designIOSTANDARD LVCMOS33 [get_ports PLL_I2C_sda_io]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_designPACKAGE_PIN W21 [get_ports PLL_I2C_ext_scl_o]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_designIOSTANDARD LVCMOS33 [get_ports PLL_I2C_ext_scl_o]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_designPACKAGE_PIN T20 [get_ports PLL_I2C_ext_sda]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]
IOSTANDARD LVCMOS33 [get_ports PLL_I2C_ext_sda]

#Reset
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMPPACKAGE_PIN T3 [currentget_design]
Code Block
languageruby
title_i_bitgen.xdc
ports reset]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWNIOSTANDARD LVCMOS15 [current_design]

Design specific constrain

Code Block
languageruby
title_i_reset.xdc
linenumberstrue
get_ports reset]
#CLKS
set_property PULLDOWNPACKAGE_PIN trueR4 [get_ports reset]
Code Block
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title_i_io.xdc
linenumberstrue
#I2C
#set{CLK1B[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {CLK1B[0]}]
set_property PACKAGE_PIN W21K4 [get_ports PLL{CLK0_I2C_scl_ioclk_p[0]}]
#setset_property IOSTANDARD LVCMOS33DIFF_SSTL15 [get_ports PLL_I2C_scl_io]
#set{CLK0_clk_p[0]}]

#ETH PHY
set_property PACKAGE_PIN T20N17 [get_ports PLLphy_I2Crst_sda_ion]
#setset_property IOSTANDARD LVCMOS33 [get_ports PLL_I2C_sda_io]
set_property PACKAGE_PIN W21phy_rst_n


Code Block
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title_i_timing.xdc
linenumberstrue
create_clock -period 8.000 -name mgt_clk0_clk_p -waveform {0.000 4.000} [get_ports PLLmgt_I2Cclk0_extclk_scl_o]
set_property IOSTANDARD LVCMOS33p]


create_clock -period 10.000 -name {CLK0_clk_p[0]} -waveform {0.000 5.000} [get_ports PLL{CLK0_I2C_ext_scl_oclk_p[0]}]
set_property PACKAGE_PIN T20create_clock -period 20.000 -name {CLK1B[0]} -waveform {0.000 10.000} [get_ports PLL_I2C_ext_sda{CLK1B[0]}]
set_property IOSTANDARD LVCMOS33create_clock -period 15.152 -name CFGMCLK -waveform {0.000 7.576} [get_ports PLL_I2C_ext_sda]

#Reset
set_property PACKAGE_PIN T3pins -hierarchical -filter {NAME =~*NO_DUAL_QUAD_MODE.QSPI_NORMAL/*STARTUP_7SERIES_GEN.STARTUP2_7SERIES_inst/CFGMCLK}]


set_false_path -from [get_ports reset]
set_property IOSTANDARD LVCMOS15 clocks {CLK0_clk_p[0]}] -to [get_ports resetclocks clk_pll_i]
#CLKS
set_property PACKAGEfalse_PINpath R4-from [get_ports {CLK1B[0]}]
set_property IOSTANDARD LVCMOS15 clocks mgt_clk0_clk_p] -to [get_ports {CLK1B[0]}clocks clk_pll_i]
set_property PACKAGEfalse_PINpath K4-from [get_portspins {CLK0_clk_p[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {CLK0_clk_p[0]}]

#ETH PHY
set_property PACKAGE_PIN N17 [get_ports phy_rst_n]
set_property IOSTANDARD LVCMOS33 [get_ports phy_rst_n
Code Block
languageruby
title_i_timing.xdc
linenumberstrue
create_clock -period 8.000 -name mgt_clk0_clk_p -waveform {0.000 4.000} [get_portsmsys_i/SC0712_0/U0/rst_delay_i_reg[3]/C}] -to [get_pins -hierarchical -filter {NAME =~*u_msys_mig_7series_0_0_mig/u_ddr3_infrastructure/rstdiv0*/PRE}]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/mig_7series_0/u_msys_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT]] -to [get_clocks mgt_clk0_clk_p]


create_clockset_false_path -period 10.000 -name {CLK0_clk_p[0]} -waveform {0.000 5.000} [get_ports {CLK0_clk_pfrom [get_clocks clk_pll_i] -to [get_clocks {msys_i/util_ds_buf_0/U0/IBUF_OUT[0]}]
createset_false_clockpath -period 20.000 -name {CLK1B[0]} -waveform {0.000 10.000} [get_ports {CLK1B[0]}]
create_clock -period 15.152 -name CFGMCLK -waveform {0.000 7.576} [get_pins -hierarchical -filter {NAME =~*NO_DUAL_QUAD_MODE.QSPI_NORMAL/*STARTUP_7SERIES_GEN.STARTUP2_7SERIES_inst/CFGMCLK}]


set_false_path -from [get_clocks {CLK0_clk_p[0]}] -to [get_clocks clk_pll_ifrom [get_pins {msys_i/labtools_fmeter_0/U0/F_reg[*]/C}] -to [get_pins {msys_i/vio_0/inst/PROBE_IN_INST/probe_in_reg_reg[*]/D}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/COUNTER_REFCLK_inst/bl.DSP48E_2/CLK] -to [get_pins {msys_i/vio_0/inst/PROBE_IN_INST/probe_in_reg_reg[*]/D}]
set_false_path -from [get_clocks mgt_clk0_clk_p] -to [get_clocks clk_pll_i]
set_false_path -frompins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CLK}] -to [get_pins {msys_i/SC0712_0/U0/rst_delay_i_reg[3]/C}] -to [get_pins -hierarchical -filter {NAME =~*u_msys_mig_7series_0_0_mig/u_ddr3_infrastructure/rstdiv0*/PRE}]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/mig_7series_0/u_msys_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT]] -to [get_clocks mgt_clk0_clk_p]
set_false_path -from [get_clocks clk_pll_i] -to [get_clocks {msys_i/util_ds_buf_0/U0/IBUF_OUT[0]}]
set_false_path -from [get_pins {msys_i/labtools_fmeter_0/U0/F_reg[*]/C}] -to [get_pins {msys_i/vio_0/inst/PROBE_IN_INST/probe_in_reg_reg[*]/D}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/COUNTER_REFCLK_inst/bl.DSP48E_2/CLK] -to [get_pins {msys_i/vio_0/inst/PROBE_IN_INST/probe_in_reg_reg[*]/D}]
set_false_path -from [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CLK}] -to [get_pins {msys_i/labtools_fmeter_0/U0/F_reg[*]/D}]

Software Design - SDK/HSI

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separate sections for different apps
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For SDK project creation, follow instructions from:

SDK Projects

Application

Template location: ./sw_lib/sw_apps/

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

Boadloader to load app or second bootloader from flash into DDR

Changes:

  • Add some vonsole outputs and changed bootloader read address.
  • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

  • Changed default Flash Typ to 5.

hello_te0712

Hello TE0712 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate u-boot.srec. Vivado to generate *.mcs

Software Design -  PetaLinux

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Description currently not available.

Config

  • Set kernel flash Address to 0x900000 and Kernel size to 0xA00000:
    (--> Subsystem Auto Hardware Settings --> Flash Settings)
    • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART0_SIZE = 0x5E0000
    • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART1_SIZE = 0x300000
    • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART2_SIZE =   0x20000
    • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART3_SIZE = 0xA00000

U-Boot

Code Block
languagejs
#include <configs/platform-auto.h>

#define CONFIG_SYS_BOOTM_LEN 0xF000000

/* ethernet - axi_ethernetlite_0 */
#undef CONFIG_PHY_XILINX
#undef XILINX_EMACLITE_BASEADDR    0x40E00000
#undef CONFIG_MII
#undef CONFIG_NET_MULTI
#undef CONFIG_NETCONSOLE    1
#undef CONFIG_SERVERIP    192.168.150.127
#undef CONFIG_IPADDR

/* PREBOOT */
#define CONFIG_PREBOOT    "echo U-BOOT for petalinux;setenv preboot; echo;"

Device Tree

Code Block
languagejs
/include/ "system-conf.dtsi"
/ {
};

/* QSPI PHY */

&axi_quad_spi_0 {
    #address-cells = <1>;
    #size-cells = <0>;
    flash0: flash@0 labtools_fmeter_0/U0/F_reg[*]/D}]

Software Design - SDK/HSI

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Note:
  • optional chapter separate

  • sections for different apps


For SDK project creation, follow instructions from:

SDK Projects

Application

Template location: ./sw_lib/sw_apps/

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2018.3 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

  • Modified Files: blconfig.h, bootloader.c
  • Changes:
    • Add some console outputs and changed bootloader read address.
    • Add bugfix for 2018.2 qspi flash (some reinitialisation)

xilisf_v5_11

TE modified 2018.3 xilisf_v5_11

  • Changed default Flash type to 5.

hello_te0712

Hello TE0712 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate u-boot.srec. Vivado to generate *.mcs

Software Design -  PetaLinux

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Note:
  • optional chapter separate

  • sections for linux

  • Add "No changes." or "Activate: and add List"



Description currently not available.

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

  • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART0_SIZE = 0x5E0000  
  • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART1_SIZE = 0x300000
  • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART2_SIZE =   0x20000
  • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART3_SIZE = 0xA00000
    • (Set kernel flash Address to 0x900000 and Kernel size to 0xA00000)

U-Boot

Start with petalinux-config -c u-boot

Changes:

  • CONFIG_ENV_IS_NOWHERE=y

  • # CONFIG_ENV_IS_IN_SPI_FLASH is not set

  • # CONFIG_NETCONSOLE is not set

  • # CONFIG_NET_TFTP_VARS is not set

  • # CONFIG_PHY_ATHEROS is not set

  • # CONFIG_PHY_BROADCOM is not set

  • # CONFIG_PHY_DAVICOM is not set

  • # CONFIG_PHY_LXT is not set

  • # CONFIG_PHY_MARVELL is not set

  • # CONFIG_PHY_MICREL is not set

  • # CONFIG_PHY_NATSEMI is not set

  • # CONFIG_PHY_REALTEK is not set

  • CONFIG_PHY_TI=y

  • CONFIG_PHY_XILINX=y

  • # CONFIG_DM_ETH is not set

  • # CONFIG_NETDEVICES is not set

Change platform-top.h:

Code Block
languagejs

#include <configs/platform-auto.h>

#define CONFIG_SYS_BOOTM_LEN 0xF000000

Device Tree

Code Block
languagejs
/include/ "system-conf.dtsi"
/ {
};

/* QSPI PHY */

&axi_quad_spi_0 {
    #address-cells = <1>;
    #size-cells = <0>;
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        spi-tx-bus-width=<1>;
        spi-rx-bus-width=<4>;
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
        spi-max-frequency = <25000000>;
    };
};


/* ETH PHY */
&axi_ethernetlite_0 {
    phy-handle = <&phy0>;
    mdio {
        compatible#address-cells = "jedec,spi-nor"<1>;
        spi-tx-bus-width=<1>#size-cells = <0>;
         spi-rx-bus-width=<4>;
phy0: phy@0 {
            regdevice_type = <0x0>"ethernet-phy";
        #address-cells    reg = <1>;
        #size-cells = <1>;
        spi-max-frequency = <25000000>;
    };
};


/* ETH PHY */
&axi_ethernetlite_0 {
    phy-handle = <&phy0>;
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy0: phy@0 {
            device_type = "ethernet-phy";
            reg = <1>;
        };
    };
};


Kernel

No changes.

Rootfs

No changes.

Applications

No changes.

Additional Software

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SI5338

Download  ClockBuilder Desktop for SI5338

  1. Install and start ClockBuilder
  2. Select SI5338
  3. Options → Open register map file
    Note: File location <design name>/misc/Si5338/RegisterMap.txt
  4. Modify settings
  5. Options → save C code header files
  6. Replace Header files from FSBL template with generated file

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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2:Copy Page Information Macro(date+user) Preview, Page Information Macro Preview
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    };
};


Kernel

Start with petalinux-config -c kernel

Changes:

  • No changes.

Rootfs

Start with petalinux-config -c rootfs

Changes:

  • No changes.

Applications

No additional application.

Additional Software

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Note:
  • Add description for other Software, for example SI CLK Builder ...
  • SI5338 and SI5345 also Link to:

SI5338

File location <design name>/misc/Si5338/Si5338-*.slabtimeproj

General documentation how you work with these project will be available on Si5338

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports



...

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titleDocument change history.

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DateDocument RevisionAuthorsDescription

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
current-version
current-version
prefixv.


Page info

...

infoTypeModified by
typeFlat

  • 2018.3 release (include design reworks)

v.30John Hartfiel
  • 2018.2 release

2018-05-25

...

v.28John Hartfiel
  • Design update

2018-05-08

...

v.27John Hartfiel
  • Know Issues
  • Documentation

2018-04-12

...

v.23John Hartfiel
  • Design Update

2018-03-28

...

v.22John Hartfiel
  • Know Issue for PCB REV01 only
  • Fix typo
  • New assembly variant
2018-02-13v.19John Hartfiel
  • Release 2017.4
2018-01-08v.16John Hartfiel
  • Add SCU source path
2017-12-15v.15John Hartfiel
  • Update Design and Description
2017-11-07v.11John Hartfiel
  • Update Design Files
2017-10-06v.10John Hartfiel
  • small Document Update
2017-10-05

v.8

John Hartfiel
  • Release 2017.2
2017-09-11v.1

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