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Template Revision 2.6

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"

...

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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

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    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

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        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
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          •  "RH" for Revision History
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        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
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        • "Table_PWR_BV" for Bank Voltages
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Table of Contents

Table of Contents

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The Trenz Electronic TEI0015 is an a commercial-grade, low cost and small size module integrated with Intel® MAX 10.  Intel MAX 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.

Refer to http://trenz.org/tei0015-info for the current online version of this manual and other available documentation.

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Notes :

...

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Note:
Use 'Key Features' description in shoping page, for example: https://shop.trenz-electronic.de/de/TE0728-04-1Q-SoC-Micromodul-mit-Xilinx-Automotive-Zynq-7020-512-MByte-DDR3L-6-x-6-cm

  • Intel® MAX 10 Commercial [10M08SAU169C8G]

    • Package: UBGA-169

      -UBGA

    • Speed Grade: C8 (Slowest)

    • Temperature:

       0°C ~ 85°C

       0°C to 85°C

    • Package compatible device 10M08...10M16 as assembly variant on request possible

  • SDRAM Memory up to

    64Mb, 166MHzDual High Speed USB to

    32 Mbyte (8Mbyte default)

  • USB 2.0 Multipurpose UART/FIFO IC

  • Quad SPI Flash, 64Mb
  • EEPROM Memory, 4Kb
  • 8x User LED 

  • USB port

  • 18 Bit

    (FT2232H)

    • 4 Kbit EEPROM Memory for FTDI configuration data
    • Micro USB Receptacle (communication and power)
  • SPI Flash - NOT INSTALLED (only special option)

  • 8x User LED 
  • 18 Bit 2MSPS Analog to Digital Converter
  • 2x SMA Female Connector

  • I/O interface: 23x GPIO - Arduino MKR compatible

  • Power Supply:

    5V

    Others
  • Dimension: 86.5mm x 25mm

    Dimension
  • Others:

  • 86m x 25m
    • Instrumentation Amplifier

  • Voltage Feedback
    • Differential Amplifier

    • Operational Amplifier

Block Diagram

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Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


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Scroll Title
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titleTEI0015 block diagram


11
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Main Components

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titleTEI0015 main components


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  1. SMA Connector, J5...6

  2. Instrumentation

    Amplifier, U12 - U14 - U6

  3. Series

    Voltage Reference, U8

  4. Analog to Digital

    Convertor

    Converter, U15

    - U6

  5. Voltage Regulator, U10 - U13 - U16

  6. Buck

    Switching Voltage Regulator/LDO, U11 - U4

  7. SDRAM Memory, U2

  8. Intel® MAX 10 FPGA, U1SDRAM Memory, U2
  9. SPI Flash Memory, U5

    USP to UART convertor
  10. 12.00 MHz MEMS oscillator, U7

  11. FTDI USB2 to JTAG/UART adapter, U3

  12. User LEDs, D2...9

  13. 4Kb

    FTDI configuration EEPROM, U9

    Switch
  14. Configuration/Status LED (Red) , D10

  15. Power-on LED (Green), D1

  16. Push button, S1...2

  17. Micro USB

    port

    Connector, J9

  18. Pin Holder

    1x14 pin header, J2 (Not assembled)

  19. 1x6 pin header, J4 (Not assembled)

  20. 1x4 Header, J3 (Not assembled)

  21. 1x14 pin header, J1

    ...4

    (Not assembled)

Initial Delivery State

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Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

...

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titleInitial delivery state of programmable devices on the module

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Not Programmed

Storage device name

Content

Notes

Quad SPI Flash

N/A

Not

Programmed

populated

I2C Configuration EEPROM

Programmed

SDRAM

FTDI configuration


Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.

The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or (using a *.POF file) on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile configuration memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up. To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile , means (using a *.SOF file), means the configuration is lost after power off.

Reset process must be done FPGA Reconfigration can be triggered by pressing push button S1.

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titleReset process.

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Signal

Push ButtonPin HeaderNote

RESET

S1J2connected Connected to nCONFIG


Signals, Interfaces and Pins

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titleGeneral I/Os to Pin Headers and connectors information

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FPGA BankConnector DesignatorI/O Signal CountVoltage LevelNotes
Bank 1AJ173.3VAIN0...6
Bank 1BJ453.3VJTAG interface
Bank 2J143.3VDIO2...5
Bank 5J293.3VDIO6...14
J123.3VDIO0...1
Bank 8J213.3VRESET


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titleFPGA I/O Banks
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FPGA BankI/O Signal CountConnected toNotes
Bank 1A71x14 Pin header, J1AIN0...6
1Jumper, J3AIN7
Bank 1B51x6 Pin header, J4JTAG_EN, TDI, TDO, TMS, TCK
Bank 2


41x14 Pin header, J1D2...5
5A2D, U15ADC_EN, ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV
112MHz Oscillator, U7CLK12M
2Amplifier, U12nIAMP_A0, nIAMP_A1
Bank 322SDRAM, U2RAM_ADDR_CMD
Bank 59

1x14 Pin header, J2

DIO6...14
21x14 Pin header, J1DIO0...1
1D12_RDIO12
Bank 616SDRAM, U2DQ0...15
2SDRAM, U2DQM0...1
1D11_RDIO11
Bank 8



8User Red LEDs, D2...9LED0...7
6SPI Flash, U5F_CS, F_
CK
CKL, F_DI, F_DO, nSTATUS, DEVCLRn
1Red LED, D10CONF_DONE
6FTDI JTAG/UART Adapter, U3BDBUS0...5
1Push Button, S2USER_BTN

JTAG Interface

...


Micro-USB Connector

The Micro-USB connector J9 provides an interface to access the FIFO/UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that FTDI USB drivers are installed on your host PC.

Scroll Title
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titleJTAG Micro USB-2 connector pins connection

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JTAG Signal

Pin Header Connector

TMSJ4-6
TDIJ4-5
TDOJ4-4
TCK

J4-3

JTAG_ENJ4-2

On-board Peripherals

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Notes :

add
PinsConnected toNote
VBUSUSB_VBUS
D+

FTDI FT2232H U3, DP pin


D-

FTDI FT2232H U3, DM pin



JTAG Interface

JTAG access to the TEI0015 SoM through pin header connector J4. This is normally not needed as there is on-board USB JTAG functionality.

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titleJTAG pins connection

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JTAG Signal

Pin Header Connector

Note
TMSJ4-6
TDIJ4-5
TDOJ4-4
TCK

J4-3


JTAG_ENJ4-2Pulled-up to 3.3V


On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

...

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titleOn board peripherals

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Chip/InterfaceDesignatorNotes
SDRAM
77530153U2
FTDI FT2232HU3JTAG/UART
Adapter
/FIFO
SPI Flash
Memory
U5
EEPROM

77530153U9
OscillatorU7
12MHz
12 MHz clock source
A2D Convertor
77530153U12, U14Analog to Digital
Convertor
Converter
Push ButtonsS1...2
8x User LEDsD2...9Red LEDs

...


SDRAM

TEI0015 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

...

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titleQuad SPI SDRAM interface MIOs IOs and pins

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SDRAM I/O Signals

Signal Schematic Name

Connected toNotes
Address inputs

A0 ... A13

bank 3-
Bank address inputs

BA0 / BA1

bank 3

-
Data input/output

DQ0 ... DQ15

bank 6

-
Data mask

DQM0 ... DQM1

bank 6

-
ClockCLKbank 3-
Control Signals

CS

bank 3

Chip select

CKE

bank 3

Clock enable

RAS

bank 3

Row Address Strobe

CAS

bank 3

Column Address Strobe

WEbank 3Write Enable


FTDI FT2232H

The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity features of the FT2232H chip.
FTDI FT2232H chip channel A is used in MPPSE mode for JTAG, 6 I/O's of . Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfacesis configured to be used in async FIFO mode, this is default mode when using preprogrammed FTDI configuration. In this mode the communication from host PC looks like normal UART but from the FTDI side it is 8 bit FIFO style interface.

The configuration of FTDI FT2232H chip is pre-programmed on in the EEPROM U9.

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titleFTDI chip interfaces and pins

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FTDI Chip U3 PinSignal Schematic NameConnected toNotes
Pin 12,
ADBUS0TCKFPGA bank 1B, pin G2JTAG interface
Pin 13, ADBUS1
ADBUS1TDIFPGA bank 1B, pin F5
Pin 14, ADBUS2
ADBUS2TDOFPGA bank 1B, pin F6
Pin 15, ADBUS3
ADBUS3TMS

FPGA bank 1B, pin G1

Pin 32,
BDBUS0BDBUS0FPGA bank 8, pin A4
user
User configurable
Pin 33, BDBUS1
BDBUS1BDBUS1FPGA bank 8, pin B4
user
User configurable
Pin 34,
BDBUS2BDBUS2FPGA bank 8, pin B5
user
User configurable
Pin 35,
BDBUS3BDBUS3FPGA bank 8, pin A6
user
User configurable
Pin 37,
BDBUS4BDBUS4FPGA bank 8, pin B6
user
User configurable
Pin 38,
BDBUS5BDBUS5FPGA bank 8, pin A7
user
User configurable

...

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MIO PinSchematicU? PinNotes
BDBUS6
Scroll Title
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titleI2C interface MIOs and pins
BDBUS6FPGA bank 6, pin C11
BDBUS7BDBUS7FPGA bank 3, pin J7
BCBUS0BCBUS0FPGA bank 5, pin J9
BCBUS1BCBUS1FPGA bank 3, pin K5
BCBUS2BCBUS2FPGA bank 3, pin L4
BCBUS3BCBUS3FPGA bank 3, pin L5
BCBUS4BCBUS4FPGA bank 3, pin N12


SPI Flash

Optional SPI flash device maybe assembled in custom variants, normally it is not populated.

Designator
Scroll Title
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titleI2C Address for RTCQuad SPI Flash memory interface

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MIO PinI2C Address
Scroll Title
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titleI2C EEPROM interface MIOs and pins
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MIO PinSchematicU?? PinNotes
Signal Schematic NameConnected toNotes

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F_CSFPGA bank 8, pin B3Chip select
F_CLKFPGA bank 8, pin A3Clock
F_DIFPGA bank 8, pin A2Data in / out
nSTATUS

FPGA bank 8, pin C4

Data in / out, configuration dual-purpose pin of FPGA
DEVCLRNFPGA bank 8, pin B9Data in / out, configuration dual-purpose pin of FPGA
F_DOFPGA bank 8, pin B2Data in / out


EEPROM

The configuration of FTDI FT2232H chip is pre-programmed in the EEPROM U9.

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titleI2C address for EEPROM interface MIOs and pins

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MIO PinI2C AddressDesignatorNotes

...

SchematicConnected toNotes

EECS

FTDI U3, Pin EECS
EECLKFTDI U3, Pin EECLK
EEDATAFTDI U3, Pin EEDATA


ADC

The TEI0015 board is equipped with the Analog Devices AD4003BCPZ-RL7 18-bit 2MSPS ADC.

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titleOn-board LEDsA2D converter interface and pins

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Schematic
Pins
Color
Connected toNotes
Active LevelNote

DDR3 SDRAM

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Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

Ethernet

IN+

Diff Amplifier U14, VOUT-
IN-Diff Amplifier U14, VOUT+
SDIFPGA, bank 2, pin M2, ADC_SDI
SDOFPGA, bank 2, pin M1,  ADC_SDO
SCKFPGA, bank 2, pin N3,  ADC_SCK
CNVFPGA, bank 2, pin N2, ADC_CNV


LEDs

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titleEthernet PHY to Zynq SoC connectionsOn-board LEDs

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Bank
Designator
Signal Name
Color
ETH1
Connected to
ETH2
Active Level
Signal Description

CAN Transceiver

...

anchorTable_OBP_CAN
titleCAN Tranciever interface MIOs

...

Note
D2...9RedLED1...8Active HighUser LEDs
D10RedCONF_DONEActive LowConfiguration DONE LED
D1Green3.3V Active HighAfter power on it will be on.


Push Bottuns

Microchip MEMS
Scroll Title
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titleOsillatorsOn-board Push Buttons

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Clock SourceSchematic NameFrequencyNote
DesignatorConnected toFunctionalityNote
S1RESETGeneral reset
S2USER_BTNUser push buttonConnected to FPGA Bank 8.


Clock Sources

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titleOsillators

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Clock SourceSchematic NameFrequencyNote
MEMS Oscillator, U7CLK12M12.00 MHz

Connected to FTDI FT2232 U3, pin 3.

Connected to FPGA SoC bank 2, pin H6.


Power and Power-On Sequence

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power supply with minimum current capability of xx A for system startup is recommendedThe module is power supplied from USB (optionally via unpopulated pin header).

Power Consumption

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titlePower Consumption

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Power Input PinFPGATypical Current
VINIntel MAX 10 10M08 FPGATBD*


* TBD - To Be Determined

Actual power consumption depends on the FPGA design and ambient temperature.

Power Distribution Dependencies

Scroll Title
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titlePower Distribution


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Power-On Sequence

...

anchorFigure_PWR_PS
titlePower Sequency
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Voltage Monitor Circuit

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titleVoltage Monitor Circuit
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Power-On Sequence

There is no specific or special power-on sequence, just one single power source is needed. After power on the green LED (D1) will be on.

Power Rails

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titleModule power rails.

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Power Rail Name
B2B

Connector

JM1

J2 Pin

B2B

Connector

JM2

J9 Pin

B2B Connector

JM3 Pin

DirectionNotes

...

scrolltitleZynq
VIN
J2-
13
anchorTable_PWR_BV
title
-Input5 V - Pin Header
3.3VJ2-12-Output
5VJ2-14-Output

USB_VBUS

-J9-1Input5 V - USB Connector


Bank Voltages

Scroll Title
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titleIntel MAX 10 SoC bank voltages.

use "include page" macro and link to the general B2B connector page of the module series,

...

? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.

Technical Specifications

Absolute Maximum Ratings

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Bank          

Schematic Name

Voltage

Notes

...

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Bank 1AVCCIO1A3.3V
Bank 1B

VCCIO1B

3.3V
Bank 2VCCIO23.3V
Bank 3VCCIO33.3V
Bank 5VCCIO53.3V
Bank 6VCCIO63.3V


Bank 8VCCIO83.3V



Technical Specifications

Absolute Maximum Ratings

V
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titlePS absolute Absolute maximum ratings

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SymbolsDescriptionMinMaxUnit
V
Reference Document
V
V

VIN 

V
Supply voltage4.755.25V
VV

...


CH1-, CH1+Analog input voltage on amplifier U12 pin 1, 10-3030VAD8251 datasheet

T_STG

Storage Temperature-25+85°C


Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

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titleRecommended operating conditions.

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Parameter
SymbolsMinMax
Units
UnitReference Document
VSee ???? datasheets.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.°CSee Xilinx ???? datasheet.°CSee Xilinx ???? datasheet.

Physical Dimensions

...

VIN supply voltage (5.0V nominal)

4.755.25V
Analog input voltage on amplifier U12 pin 1 (CH1-), 10 (CH1+)-1010VAD8251 datasheet

T_OP

0+70°CW9864G6JT-6 datasheet


Physical Dimensions

Module size: 25 mm × 86.5 mm.  Please download the assembly diagram for exact numbers

...

.

PCB thickness: ?? 1.22 mm.

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In 'Physical Dimension' section, top and button view of moduloe must be insterted, information regarding physical dimention can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part)for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


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Scroll Title
anchorFigure_TS_PD
titlePhysical Dimension
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idComments


scroll-eclipsehelp
Scroll Ignore

Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue

draw.io Diagram
borderfalse
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diagramNameTEI0015_TS_PD
simpleViewerfalse
linksauto
tbstylehidden
lboxtrue
diagramWidth641
revision1


Scroll Only
scroll-pdftrue
scroll-epubofficetrue
scroll-htmlchmtrue

image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Currently Offered Variants 

scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue

Image Added


Currently Offered Variants 

Page properties
hiddentrue
idComments

Set correct link to the shop page overview table of the product on English and German.

Example for TE0728:

ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

if not available, set.

  • https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/

  • https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/

    .


    Scroll Title
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    titleTrenz Electronic Shop Overview

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    Trenz shop TEI0015 overview page
    English pageGerman page


    Revision History

    Hardware Revision History

    Scroll Title
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    titleHardware Revision History

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    DateRevisionChangesDocumentation Link
    2019-02-1101-REV01


    Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

    -
    Scroll Title
    anchorTableFigure_VCPRV_SOHRN
    titleTrenz Electronic Shop Overview Board hardware revision number.


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    draw.io Diagram

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    Scroll Title
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    titleHardware Revision History
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    DateRevisionChanges

    false

    widthssortByColumn1sortEnabledfalsecellHighlightingtrueTrenz shop TE0728 overview pageEnglish pageGerman page

    Revision History

    Hardware Revision History

    List of online PCN ...Link

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    Scroll Only
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    scroll-docbooktrue
    scroll-eclipsehelptrue
    scroll-epubtrue
    scroll-htmltrue

    Image Added


    Document Change History

    Page properties
    hiddentrue
    idComments
    • Note this list must be only updated, if the document is online on public doc!
    • It's semi automatically, so do following
      • Add new row below first

      • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

      • Metadata is only used of compatibility of older exports

    ...

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    titleDocument change history.

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    change list

    • multiple sections updated

    2020-02-04

    v.98ED
    • Technical Specifications updated

    • Power Rails updated

    --

    all

    Page info
    infoTypeModified users
    typeFlat
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    • --


    ...