Versions Compared

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

Page properties
hiddentrue
idComments

Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:

        Scroll Title
        anchorFigure_anchorname
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • Scroll Title
        anchorTable_tablename
        titleText

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefaultstyle
        widthssortByColumn1
        sortEnabledfalse
        cellHighlightingtrue

        ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>


...

Page properties
hiddentrue
idComments

Note for Download Link of the Scroll ignore macro:


Scroll Ignore

Download PDF version of this document.


Scroll pdf ignore

Table of Contents

Table of Contents

...

  • Intel® MAX 10 Commercial [10M08SAU169C8G]

    • Package: UBGA-169

    • Speed Grade: C8 (Slowest)

    • Temperature: 0°C ~ to 85°C

    • Package compatible device 10M0210M08...10M16 as assembly variant on request possible

  • SDRAM Memory up to 64Mb, 166MHzDual High Speed USB to 32 Mbyte (8Mbyte default)

  • USB 2.0 Multipurpose UART/FIFO IC

  • Quad SPI Flash, 64Mb

  • EEPROM Memory, 4Kb

    (FT2232H)

    • 4 Kbit EEPROM Memory for FTDI configuration data
    • Micro USB Receptacle (communication and power)
  • SPI Flash - NOT INSTALLED (only special option)

  • 8x User LED Micro USB2 Receptacle 90
  • 18 Bit 2MSPS Analog to Digital Converter
  • 2x SMA Female Connector

  • I/O interface:

  • 250x GPIO

  • 116x LVDS

    23x GPIO - Arduino MKR compatible

  • Power Supply: 5V

  • Minimum 1A

  • Dimension: 86.5mm x 25mm

  • Others:

    • Instrumentation Amplifier

    • Differential Amplifier

    • Operational Amplifier

...

Scroll Title
anchorFigure_OV_BD
titleTEI0015 block diagram


Scroll Ignore
draw.io Diagram
width
borderfalse
viewerToolbartrue
fitWindowfalsediagramDisplayName
lboxtrue
revision20
diagramNameTEI0015_OV_BD
simpleViewerfalse
linksauto
tbstylehidden
lboxtrue
diagramWidth642
revision64127


Scroll Only


Main Components

...

Scroll Title
anchorFigure_OV_BD
titleTEI0015 main components


Scroll Ignore

draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalsediagramDisplayName
lboxtrue
revision13
diagramNameTEI0015_OV_MC
simpleViewerfalse
widthlinksauto
tbstylehidden
lboxtrue
diagramWidth641
revision14


Scroll Only


  1. SMA Connector, J5...6

  2. Amplifier, U12 - U14 - U6

  3. Series Voltage Reference, U8

  4. Analog to Digital ConvertorConverter, U15

  5. Voltage Regulator, U10 - U13 - U16

  6. Switching Voltage Regulator/LDO, U11 - U4

  7. SDRAM Memory, U2

  8. Intel® MAX 10 FPGA, U1SDRAM Memory, U2
  9. SPI Flash Memory, U5

  10. 12.00 MHz MEMS oscillator, U7

  11. FTDI USB2 to JTAG/UART adapter, U3

  12. User LEDs, D2...9

  13. 4Kb FTDI configuration EEPROM, U9

  14. Configuration/Status LED (Red) , D10

  15. Power-on LED (Green), D1

  16. Push button, S1...2

  17. Micro USB2 ReceptacleUSB Connector, J9

  18. 1x14 pin header header, J2 (Not assembled), J2

  19. 1x6 pin header header, J4 (Not assembled), J4

  20. Jumper1x4 Header, J3 (Not assembled)

  21. 1x14 pin header header, J1 (Not assembled), J1

Initial Delivery State

Page properties
hiddentrue
idComments

Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

...

Scroll Title
anchorTable_OV_IDS
titleInitial delivery state of programmable devices on the module

Scroll Table Layout
widths
orientationportrait
sortDirectionASC
repeatTableHeadersdefaultstyle
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Not Programmed

Storage device name

Content

Notes

Quad SPI Flash

N/A

Not

Programmed

populated

EEPROM

Programmed

FTDI configuration

SDRAM


Configuration Signals

Page properties
hiddentrue
idComments
  • Overview of Boot Mode, Reset, Enables.

The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or (using a *.POF file) on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile configuration memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up. To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile (using a *.SOF file), means the configuration is lost after power off.

Reset process must be done FPGA Reconfigration can be triggered by pressing push button S1.

Scroll Title
anchorTable_OV_RST
titleReset process.

Scroll Table Layout
widths
orientationportrait
sortDirectionASC
repeatTableHeadersdefaultstyle
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Signal

Push ButtonPin HeaderNote

RESET

S1J2connected Connected to nCONFIG


Signals, Interfaces and Pins

...

Scroll Title
anchorTable_SIP_GIOs
titleGeneral I/Os to Pin Headers and connectors information

Scroll Table Layout
widths
orientationportrait
sortDirectionASC
repeatTableHeadersdefaultstyle
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

FPGA BankConnector DesignatorI/O Signal CountVoltage LevelNotes
Bank 1AJ173.3VAIN0...6
Bank 1BJ453.3VJTAG interface
Bank 2J143.3VDIO2...5
Bank 5J293.3VDIO6...14
J123.3VDIO0...1
Bank 8J213.3VRESET


...

Scroll Title
anchorTable_OBP_IOs
titleFPGA I/O Banks


FPGA BankI/O Signal CountConnected toNotes
Bank 1A71x14 Pin header, J1AIN0...6
1Jumper, J3AIN7
Bank 1B51x6 Pin header, J4JTAG_EN, TDI, TDO, TMS, TCK
Bank 2


41x14 Pin header, J1D2...5
5A2D, U15ADC_EN, ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV
112MHz Oscillator, U7CLK12M
2Amplifier, U12nIAMP_A0, nIAMP_A1
Bank 322SDRAM, U2RAM_ADDR_CMD
Bank 59

1x14 Pin header, J2

DIO6...14
21x14 Pin header, J1DIO0...1
1D12_RDIO12
Bank 616SDRAM, U2DQ0...15
2SDRAM, U2DQM0...1
1D11_RDIO11
Bank 8



8User Red LEDs, D2...9LED0...7
6SPI Flash, U5F_CS, F_CKCKL, F_DI, F_DO, nSTATUS, DEVCLRn
1Red LED, D10CONF_DONE
6FTDI JTAG/UART Adapter, U3BDBUS0...5
1Push Button, S2USER_BTN


Micro

...

-USB Connector

The Micro-USB2 USB connector J9 provides an interface to access the FIFO/UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that FTDI USB driver is drivers are installed on your host PC.

Scroll Title
anchorTable_OBP_USB
titleMicro USB-2 connector pins

Scroll Table Layout
widths
orientationportrait
sortDirectionASC
repeatTableHeadersdefaultstyle
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

It is connected to GND
PinsConnected toNote
VBUSUSB_VBUS
D+

FTDI FT2232H U3, DP pin


D-

FTDI FT2232H U3, DM pin



JTAG Interface

JTAG access to the TEI0015 SoM through pin header connector J4. This is normally not needed as there is on-board USB JTAG functionality.

Scroll Title
anchorTable_SIP_JTG
titleJTAG pins connection

Scroll Table Layout
style
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
widthssortByColumn1
sortEnabledfalse
cellHighlightingtrue

JTAG Signal

Pin Header Connector

Note
TMSJ4-6
TDIJ4-5
TDOJ4-4
TCK

J4-3


JTAG_ENJ4-2Pulled-up to 3.3V


On-board Peripherals

Page properties
hiddentrue
idComments

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

...

Scroll Title
anchorTable_OBP
titleOn board peripherals

Scroll Table Layout
widths
orientationportrait
sortDirectionASC
repeatTableHeadersdefaultstyle
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Chip/InterfaceDesignatorNotes
SDRAM
77530153U2
FTDI FT2232HU3JTAG/UART
Adapter
/FIFO
SPI Flash
Memory
U5
EEPROM

77530153U9
OscillatorU7
12MHz
12 MHz clock source
ADC
77530153U12, U14Analog to Digital Converter
Push ButtonsS1...2
8x User LEDsD2...9Red LEDs


SDRAM

TEI0015 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

...

Scroll Title
anchorTable_OBP_SDRAM
titleSDRAM interface IOs and pins

Scroll Table Layout
widths
orientationportrait
sortDirectionASC
repeatTableHeadersdefaultstyle
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

SDRAM I/O Signals

Signal Schematic Name

Connected toNotes
Address inputs

A0 ... A13

bank 3-
Bank address inputs

BA0 / BA1

bank 3

-
Data input/output

DQ0 ... DQ15

bank 6

-
Data mask

DQM0 ... DQM1

bank 6

-
ClockCLKbank 3-
Control Signals

CS

bank 3

Chip select

CKE

bank 3

Clock enable

RAS

bank 3

Row Address Strobe

CAS

bank 3

Column Address Strobe

WEbank 3Write Enable


FTDI FT2232H

The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity features of the FT2232H chip. FTDI FT2232H chip channel A is used in MPPSE mode for JTAG, 6 I/O's of . Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfacesis configured to be used in async FIFO mode, this is default mode when using preprogrammed FTDI configuration. In this mode the communication from host PC looks like normal UART but from the FTDI side it is 8 bit FIFO style interface.

The configuration of FTDI FT2232H chip is pre-programmed on in the EEPROM U9.

Scroll Title
anchorTable_OBP_FTDI
titleFTDI chip interfaces and pins

EEPROM

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

I2C EEPROM interface MIOs and pins
Scroll Title
anchorTable_OBP_EEP
title

Scroll Table Layout
style
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
widthssortByColumn1
sortEnabledfalse
cellHighlightingtrue

FTDI Chip U3 PinSignal Schematic NameConnected toNotes
ADBUS0TCKFPGA bank 1B, pin G2JTAG interface
ADBUS1TDIFPGA bank 1B, pin F5
ADBUS2TDOFPGA bank 1B, pin F6
ADBUS3TMS

FPGA bank 1B, pin G1

BDBUS0BDBUS0FPGA bank 8, pin A4user User configurable
BDBUS1BDBUS1FPGA bank 8, pin B4user User configurable
BDBUS2BDBUS2FPGA bank 8, pin B5user User configurable
BDBUS3BDBUS3FPGA bank 8, pin A6user User configurable
BDBUS4BDBUS4FPGA bank 8, pin B6user User configurable
BDBUS5BDBUS5FPGA bank 8, pin A7user User configurable
BDBUS6

SPI Flash Memory

On-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interface.

...

anchorTable_OBP_QSPI
titleQuad SPI Flash memory interface

...

FPGA bank 8, pin C4

...

BDBUS6FPGA bank 6, pin C11
BDBUS7BDBUS7FPGA bank 3, pin J7
BCBUS0BCBUS0FPGA bank 5, pin J9
BCBUS1BCBUS1FPGA bank 3, pin K5
BCBUS2BCBUS2FPGA bank 3, pin L4
BCBUS3BCBUS3FPGA bank 3, pin L5
BCBUS4BCBUS4FPGA bank 3, pin N12


SPI Flash

Optional SPI flash device maybe assembled in custom variants, normally it is not populated.

Scroll Title
anchorTable_OBP_QSPI
titleQuad SPI Flash memory interface

Scroll Table Layout
widths
orientationportrait
sortDirectionASC
repeatTableHeadersdefaultstyle
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Signal Schematic NameConnected toNotes

EECS

FTDI U3, Pin EECSEECLKFTDI U3, F_CSFPGA bank 8, pin B3Chip select
F_CLKFPGA bank 8, pin A3Clock
F_DIFPGA bank 8, pin A2Data in / out
nSTATUS

FPGA bank 8, pin C4

Data in / out, configuration dual-purpose pin of FPGA
DEVCLRNFPGA bank 8, pin B9Data in / out, configuration dual-purpose pin of FPGA
F_DOFPGA bank 8, pin B2Data in / out


EEPROM

The configuration of FTDI FT2232H chip is pre-programmed in the EEPROM U9.

Scroll Title
anchorTable_OBP_EEP
titleI2C EEPROM interface MIOs and pins

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

SchematicConnected toNotes

EECS

FTDI U3, Pin EECS
EECLKFTDI U3, Pin EECLK
EEDATAFTDI U3, Pin EEDATA


...

The TEI0015 board is equipped with the 18the Analog Devices AD4003BCPZ-RL7 18-bit 2MSPS ADC provided by Analog Devices, .

Scroll Title
anchorTable_OBP_A2D
titleA2D converter interface and pins

Scroll Table Layout
widths
orientationportrait
sortDirectionASC
repeatTableHeadersdefaultstyle
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

PinsConnected toNotes

IN+

Diff Amplifier U14, VOUT-
IN-Diff Amplifier U14, VOUT+
SDIBank 2FPGA, bank 2, pin M2, ADC_SDI
SDOBank FPGA, bank 2, ADCpin M1,  ADC_SDO
SCKBank FPGA, bank 2, ADCpin N3,  ADC_SCK
CNVBank 2FPGA, bank 2, pin N2, ADC_CNV


LEDs

Scroll Title
anchorTable_OBP_LED
titleOn-board LEDs

Scroll Table Layout
widths
orientationportrait
sortDirectionASC
repeatTableHeadersdefaultstyle
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DesignatorColorConnected toActive LevelNote
D2...9RedLED1...8Active HighUser LEDs
D10RedCONF_DONEActive LowConfiguration DONE LED
D1Green3.3V Active HighAfter power on it will be on.


Push Bottuns

Scroll Title
anchorTable_OBP_LED
titleOn-board Push Buttons

Scroll Table Layout
widths
orientationportrait
sortDirectionASC
repeatTableHeadersdefaultstyle
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DesignatorConnected toFunctionalityNote
S1RESETGeneral reset
S2USER_BTNUser push buttonConnected to FPGA Bank 8.


Clock Sources

Scroll Title
anchorTable_OBP_CLK
titleOsillators

Scroll Table Layout
widths
orientationportrait
sortDirectionASC
repeatTableHeadersdefaultstyle
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Clock SourceSchematic NameFrequencyNote
Microchip MEMS Oscillator, U7CLK12M12.00 MHz

Connected to FTDI FT2232 U3, pin 3.

Connected to FPGA SoC bank 2, pin H6.


Power and Power-On Sequence

Page properties
hiddentrue
idComments

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

To power-up the module, power supply with minimum current capability of 1A is recommendedThe module is power supplied from USB (optionally via unpopulated pin header).

Power Consumption

Scroll Title
anchorTable_PWR_PC
titlePower Consumption

Scroll Table Layout
widths
orientationportrait
sortDirectionASC
repeatTableHeadersdefaultstyle
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

FPGATypical Current
Intel MAX 10 10M08 FPGA SoCFPGATBD*


* TBD - To Be Determined

...

Scroll Title
anchorFigure_PWR_PD
titlePower Distribution


Scroll Ignore

draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
diagramDisplayNameTEI0015_PWR_P
lboxfalse
viewerToolbartrue
revisionfitWindow10false
diagramNameTEI0015_PWR_PD
simpleViewerfalse
widthlinksauto
tbstylehidden
diagramDisplayNameTEI0015_PWR_P
lboxtrue
diagramWidth638
revision12


Scroll Only


Power-On Sequence

There is no specific or special power-on sequence, just one single power source is needed. After power on the Green green LED (D1) will be on.

Power Rails

Voltage
Scroll Title
anchorTable_PWR_PR
titleModule power rails.

Scroll Table Layout
widths
orientationportrait
sortDirectionASC
repeatTableHeadersdefaultstyle
sortByColumn1
sortEnabledfalse
cellHighlightingtrue


Power Rail Name

Connector

Designator
VCC / VCCIO Schematic Name

J2 Pin

Connector

J9 Pin

DirectionNotes
VINJ2-13
VIN
-
5VInput
Input5 V - Pin Header
3.3V
3.3V
J2-12-Output
5V
5V
J2-14-Output

J9


USB_VBUS

-
5V
J9-1Input5 V - USB Connector


Bank Voltages

Scroll Title
anchorTable_PWR_BV
titleZynq Intel MAX 10 SoC bank voltages.

Scroll Table Layout
style
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
widthssortByColumn1
sortEnabledfalse
cellHighlightingtrue

Bank          

Schematic Name

Voltage

Notes
Bank 1AVCCIO1A3.3V
Bank 1B

VCCIO1B

3.3V
Bank 2VCCIO23.3V
Bank 3VCCIO33.3V
Bank 5VCCIO53.3V
Bank 6VCCIO63.3V


Bank 8VCCIO83.3V



Technical Specifications

Absolute Maximum Ratings

...

anchorTable_TS_AMR
titleAbsolute maximum ratings

...

VIN 

...

Supply voltage for input and output buffers

...

Scroll Title
anchorTable_TS_AMR
titleAbsolute maximum ratings

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

SymbolsDescriptionMinMaxUnitReference Document

VIN 

Supply voltage4.755.25V
CH1-, CH1+Analog input voltage on amplifier U12 pin 1, 10-3030VAD8251 datasheet

T_STG

Storage Temperature-25+85°C


Recommended Operating Conditions

...

see AD4003BCPZ

Scroll Title
anchorTable_TS_ROC
titleRecommended operating conditions.

Scroll Table Layout
widths
orientationportrait
sortDirectionASC
repeatTableHeadersdefaultstyle
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

SymbolsMinMaxUnitReference Document

VIN supply voltage (5.0V nominal)

4.755.25V
VCC_ONE3.1353.456Vsee Intel MAX 10 datasheet
VCCIO3.1353.456Vsee Intel MAX 10 datasheet
VCCA3.1353.456Vsee Intel MAX 10 datasheet
V_AN_IN-0.15.1Vsee AD4003BCPZ datasheet
V_REF2.45.1V
true

SymbolsMinMaxUnitReference Document

VIN supply voltage (5.0V nominal)

4.755.25V
Analog input voltage on amplifier U12 pin 1 (CH1-), 10 (CH1+)-1010VAD8251 datasheet

T_OP

0+70°CW9864G6JT-6 datasheet


Physical Dimensions

Module size: 25 mm × 86.5 mm.  Please download the assembly diagram for exact numbers.

...

Scroll Title
anchorFigure_TS_PD
titlePhysical Dimension


Scroll Ignore

draw.io Diagram
revisionwidth
borderfalse
viewerToolbartrue
fitWindowfalsediagramDisplayName
lboxtrue
1
diagramNameTEI0015_TS_PD
simpleViewerfalse
linksauto
tbstylehidden
lboxtrue
diagramWidth641
revision1


Scroll Only
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


...

Scroll Title
anchorTable_VCP_SO
titleTrenz Electronic Shop Overview

Scroll Table Layout
widths
orientationportrait
sortDirectionASC
repeatTableHeadersdefaultstyle
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Trenz shop TEI0015 overview page
English pageGerman page


...

Scroll Title
anchorTable_RH_HRH
titleHardware Revision History

Scroll Table Layout
widths
orientationportrait
sortDirectionASC
repeatTableHeadersdefaultstyle
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DateRevisionChangesDocumentation Link
2019-02-1101-REV01


...

Scroll Title
anchorFigure_RV_HRN
titleBoard hardware revision number.


Scroll Ignore

draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalsediagramDisplayName
lboxtrue
revision2
diagramNameTEI0015_RH_RHN
simpleViewerfalse
widthlinksauto
tbstylehidden
lboxtrue
diagramWidth158
revision2


Scroll Only
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


...

Scroll Title
anchorTable_RH_DCH
titleDocument change history.

Scroll Table Layout
widths
orientationportrait
sortDirectionASC
repeatTableHeadersdefaultstyle
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DateRevisionContributorDescription

Page info
infoTypeModified date
dateFormatyyyy-MM-dd
typeFlat

Page info
infoTypeCurrent version
prefixv.
typeFlat
showVersionsfalse

Page info
infoTypeModified by
typeFlat
showVersionsfalse

change list

  • multiple sections updated

2020-02-04

v.98ED
  • Technical Specifications updated

  • Power Rails updated

--

all

Page info
infoTypeModified users
typeFlat
showVersionsfalse

  • --


...