Page History

...

Page properties
hidden true id Comments
Notes : add subsection for every component which is important for design, for example: Two 100 Mbit Ethernet Transciever PHY USB PHY Programmable Clock Generator Oscillators eMMCs RTC FTDI ... DIP-Switches Buttons LEDs

Page properties
hidden true id Comments
Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

...

anchor	Table_OBP
title	On board peripherals

...

Quad SPI Flash Memory

Page properties
hidden true id Comments
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

...

anchor	Table_OBP_SPI
title	Quad SPI interface MIOs and pins

MIO12...14 SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK J2 QSPI

Scroll Title
anchor Table_OBP_IOs title FPGA I/O Banks
FPGA Bank I/O Signal Count Connected to Notes Bank 1A 7 1x14 Pin header, J1 AIN0...6 1 Jumper, J3 AIN7 Bank 1B 5 1x6 Pin header, J4 JTAG_EN, TDI, TDO, TMS, TCK Bank 2 4 1x14 Pin header, J1 D2...5 5 A2D, U15 ADC_EN, ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV 1 12MHz Oscillator, U7 CLK12M 2 Amplifier, U12 nIAMP_A0, nIAMP_A1 Bank 3 22 SDRAM, U2 RAM_ADDR_CMD Bank 5 9 1x14 Pin header, J2 DIO6...14 2 1x14 Pin header, J1 DIO0...1 1 D12_R DIO12 Bank 6 16 SDRAM, U2 DQ0...15 2 SDRAM, U2 DQM0...1 1 D11_R DIO11 Bank 8 8 User Red LEDs, D2...9 LED0...7 6 SPI Flash, U5 F_CS, F_CKL, F_DI, F_DO, nSTATUS, DEVCLRn 1 Red LED, D10 CONF_DONE 6 FTDI JTAG/UART Adapter, U3 BDBUS0...5 1 Push Button, S2 USER_BTN

Micro-USB Connector

The Micro-USB connector J9 provides an interface to access the FIFO/UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that FTDI USB drivers are installed on your host PC.

Scroll Title
anchor Table_OBP_USB title Micro USB-2 connector

...

Scroll Title
anchor Table_OBP_RTC title I2C interface MIOs and pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true MIO Pin Pins	Schematic	U? Pin	Notes
Scroll Title
Connected to Note VBUS USB_VBUS D+ FTDI FT2232H U3, DP pin D- FTDI FT2232H U3, DM pin

JTAG Interface

JTAG access to the TEI0015 SoM through pin header connector J4. This is normally not needed as there is on-board USB JTAG functionality.

Scroll Title
anchor Table_OBPSIP_I2C_RTCJTG title I2C Address for RTCJTAG pins connection
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true MIO JTAG Signal Pin Header Connector I2C Address Note Designator TMS Notes J4-6

...

scrolltitle

TDI
J4-
5
anchor Table_OBP_EEP title I2C EEPROM interface MIOs and pins
Scroll Table Layout
orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style	widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true
MIO Pin	Schematic	U?? Pin	Notes
Scroll Title
anchor Table_OBP_I2C_EEPROM title I2C address for EEPROM
Scroll Table Layout
orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style	widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true
MIO Pin	I2C Address	Designator	Notes

LEDs

TDO J4-4 TCK J4-3 JTAG_EN J4-2 Pulled-up to 3.3V

On-board Peripherals

Page properties
hidden true id Comments
Notes : add subsection for every component which is important for design, for example: Two 100 Mbit Ethernet Transciever PHY USB PHY Programmable Clock Generator Oscillators eMMCs RTC FTDI ... DIP-Switches Buttons LEDs

Page properties
hidden true id Comments
Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

Scroll Title
anchor Table_OBP_LED title On - board LEDsperipherals
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Schematic Chip/Interface Color Designator	Connected to	Active Level	Note

DDR3 SDRAM

Page properties
hidden true id Comments
Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

• Part number: 
• Supply voltage:
• Speed: 
• NOR Flash
• Temperature: 

Ethernet

...

anchor	Table_OBP_ETH
title	Ethernet PHY to Zynq SoC connections

Notes 77530153 U2 FTDI FT2232H U3 JTAG/UART/FIFO SPI Flash U5 77530153 U9 Oscillator U7 12 MHz clock source 77530153 U12, U14 Analog to Digital Converter Push Buttons S1...2 8x User LEDs D2...9 Red LEDs

SDRAM

TEI0015 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

Page properties
hidden true id Comments
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

...

CAN Transceiver

Scroll Title
anchor Table_OBP_CANSDRAM title CAN Tranciever interface MIOsSDRAM interface IOs and pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Bank SDRAM I/O Signals Signal Schematic U?? Pin Name Connected to Notes	D-Tx	Driver Input	R-Rx	Reciever Output

...

anchor	Table_OBP_CLK
title	Osillators

...

Power and Power-On Sequence

...

hidden	true
id	Comments

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

• Power on-sequence
• Power distribution
• Voltage monitoring circuit

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Power Supply

Power supply with minimum current capability of xx A for system startup is recommended.

Power Consumption

...

anchor	Table_PWR_PC
title	Power Consumption

...

* TBD - To Be Determined

Power Distribution Dependencies

...

anchor	Figure_PWR_PD
title	Power Distribution

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Address inputs A0 ... A13 bank 3 - Bank address inputs BA0 / BA1 bank 3 - Data input/output DQ0 ... DQ15 bank 6 - Data mask DQM0 ... DQM1 bank 6 - Clock CLK bank 3 - Control Signals CS bank 3 Chip select CKE bank 3 Clock enable RAS bank 3 Row Address Strobe CAS bank 3 Column Address Strobe WE bank 3 Write Enable

FTDI FT2232H

The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the features of the FT2232H chip. FTDI FT2232H chip channel A is used in MPPSE mode for JTAG. Channel B is configured to be used in async FIFO mode, this is default mode when using preprogrammed FTDI configuration. In this mode the communication from host PC looks like normal UART but from the FTDI side it is 8 bit FIFO style interface.

The configuration of FTDI FT2232H chip is pre-programmed in the EEPROM U9.

Scroll Title
anchor Table_OBP_FTDI title FTDI chip interfaces and pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true FTDI Chip U3 Pin Signal Schematic Name Connected to Notes ADBUS0 TCK FPGA bank 1B, pin G2 JTAG interface ADBUS1 TDI FPGA bank 1B, pin F5 ADBUS2 TDO FPGA bank 1B, pin F6 ADBUS3 TMS FPGA bank 1B, pin G1 BDBUS0 BDBUS0 FPGA bank 8, pin A4 User configurable BDBUS1 BDBUS1 FPGA bank 8, pin B4 User configurable BDBUS2 BDBUS2 FPGA bank 8, pin B5 User configurable BDBUS3 BDBUS3 FPGA bank 8, pin A6 User configurable BDBUS4 BDBUS4 FPGA bank 8, pin B6 User configurable BDBUS5 BDBUS5 FPGA bank 8, pin A7 User configurable BDBUS6 BDBUS6 FPGA bank 6, pin C11 BDBUS7 BDBUS7 FPGA bank 3, pin J7 BCBUS0 BCBUS0 FPGA bank 5, pin J9 BCBUS1 BCBUS1 FPGA bank 3, pin K5 BCBUS2 BCBUS2 FPGA bank 3, pin L4 BCBUS3 BCBUS3 FPGA bank 3, pin L5 BCBUS4 BCBUS4 FPGA bank 3, pin N12

SPI Flash

Optional SPI flash device maybe assembled in custom variants, normally it is not populated.

Scroll Title
anchor Table_OBP_QSPI title Quad SPI Flash memory interface
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true Signal Schematic Name Connected to Notes F_CS FPGA bank 8, pin B3 Chip select F_CLK FPGA bank 8, pin A3 Clock F_DI FPGA bank 8, pin A2 Data in / out nSTATUS FPGA bank 8, pin C4 Data in / out, configuration dual-purpose pin of FPGA DEVCLRN FPGA bank 8, pin B9 Data in / out, configuration dual-purpose pin of FPGA F_DO FPGA bank 8, pin B2 Data in / out

EEPROM

The configuration of FTDI FT2232H chip is pre-programmed in the EEPROM U9.

Scroll Title
anchor Table_OBP_EEP title I2C EEPROM interface MIOs and pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true Schematic Connected to Notes EECS FTDI U3, Pin EECS EECLK FTDI U3, Pin EECLK EEDATA FTDI U3, Pin EEDATA

ADC

The TEI0015 board is equipped with the Analog Devices AD4003BCPZ-RL7 18-bit 2MSPS ADC.

Scroll Title
anchor Table_OBP_A2D title A2D converter interface and pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true Pins Connected to Notes IN+ Diff Amplifier U14, VOUT- IN- Diff Amplifier U14, VOUT+ SDI FPGA, bank 2, pin M2, ADC_SDI SDO FPGA, bank 2, pin M1,  ADC_SDO SCK FPGA, bank 2, pin N3,  ADC_SCK CNV FPGA, bank 2, pin N2, ADC_CNV

LEDs

Scroll Title
anchor Table_OBP_LED title On-board LEDs
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true Designator Color Connected to Active Level Note D2...9 Red LED1...8 Active High User LEDs D10 Red CONF_DONE Active Low Configuration DONE LED D1 Green 3.3V  Active High After power on it will be on.

Push Bottuns

Scroll Title
anchor Table_OBP_LED title On-board Push Buttons
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true Designator Connected to Functionality Note S1 RESET General reset S2 USER_BTN User push button Connected to FPGA Bank 8.

Clock Sources

Scroll Title
anchor Table_OBP_CLK title Osillators
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true Clock Source Schematic Name Frequency Note MEMS Oscillator, U7 CLK12M 12.00 MHz Connected to FTDI FT2232 U3, pin 3. Connected to FPGA SoC bank 2, pin H6.

Power and Power-On Sequence

Page properties
hidden true id Comments
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: Power on-sequence Power distribution Voltage monitoring circuit Note For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Power Supply

The module is power supplied from USB (optionally via unpopulated pin header).

Power Consumption

Scroll Title
anchor Table_PWR_PC title Power Consumption
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true FPGA Typical Current Intel MAX 10 10M08 FPGA TBD*

* TBD - To Be Determined

Actual power consumption depends on the FPGA design and ambient temperature.

Power Distribution Dependencies

Power-On Sequence

...

anchor	Figure_PWR_PS
title	Power Sequency

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

...

Scroll Title
anchor Figure_PWR_VMCPD title Voltage Monitor CircuitPower Distribution
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed Scroll Ignore Create DrawIO object here: Attention if you copy from other page, objects are only linked. Scroll Only draw.io Diagram border false viewerToolbar true fitWindow false diagramName TEI0015_PWR_PD simpleViewer false links auto tbstyle hidden diagramDisplayName TEI0015_PWR_P lbox true diagramWidth 638 revision 12 Scroll Only Image Added

Power-On Sequence

There is no specific or special power-on sequence, just one single power source is needed. After power on the green LED (D1) will be on.

Power Rails

Notes

Scroll Title
anchor Table_PWR_PR title Module power rails.
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default stylewidths default sortByColumn 1 sortEnabled false cellHighlighting true Power Rail Name B2B Connector JM1 J2 Pin B2B Connector JM2 Pin J9 Pin Direction Notes VIN J2-13 - Input 5 V - Pin Header 3.3V J2-12 - Output 5V J2-14 - Output USB_VBUS - J9-1 Input 5 V - USB Connector	B2B Connector JM3 Pin	Direction