Page History

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• Intel® MAX 10 Commercial [10M08SAU169C8G]

  • Package: UBGA-169

  • Speed Grade: C8 (Slowest)

  • Temperature: 0°C ~ to 85°C

  • Package compatible device 10M0210M08...10M16 as assembly variant on request possible

• SDRAM Memory up to 64Mb, 166MHzDual High Speed USB to 32 Mbyte (8Mbyte default)

• USB 2.0 Multipurpose UART/FIFO IC

• 64 Mb Quad SPI Flash

• (FT2232H)

  • 4 Kbit EEPROM Memory for FTDI configuration data
  • Micro USB Receptacle (communication and power)

• SPI Flash - NOT INSTALLED (only special option)4Kb EEPROM Memory

• 8x User LED Micro USB2 Receptacle 90
• 18 Bit 2MSPS Analog to Digital Converter

• 2x SMA Female Connector

• I/O interface: 23x GPIO - Arduino MKR compatible

• Power Supply: 5V

• Minimum 1A

• Dimension: 86.5mm x 25mm

• Others:

  • Instrumentation Amplifier

  • Differential Amplifier

  • Operational Amplifier

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Main Components

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1. SMA Connector, J5...6

2. Amplifier, U12 - U14 - U6

3. Series Voltage Reference, U8

4. Analog to Digital ConvertorConverter, U15

5. Voltage Regulator, U10 - U13 - U16

6. Switching Voltage Regulator/LDO, U11 - U4

7. SDRAM Memory, U2

8. Intel® MAX 10 FPGA, U1

9. Active serial SPI Flash Memory, U5

10. 12.00 MHz MEMS oscillator, U7

11. FTDI USB2 to JTAG/UART adapter, U3

12. User LEDs, D2...9

13. 4Kb FTDI configuration EEPROM, U9

14. Configuration/Status LED (Red) , D10

15. Power-on LED (Green), D1

16. Push button, S1...2

17. Micro USB2 ReceptacleUSB Connector, J9

18. 1x14 pin header header, J2 (Not assembled), J2

19. 1x6 pin header header, J4 (Not assembled), J4

20. Jumper1x4 Header, J3 1x14 pin header  (Not assembled)

21. 1x14 pin header, J1 (Not assembled)

Initial Delivery State

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Configuration Signals

The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or (using a *.POF file) on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile configuration memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up. To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile (using a *.SOF file), means the configuration is lost after power off.

Reset process must be done FPGA Reconfigration can be triggered by pressing push button S1.

Signals, Interfaces and Pins

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Micro

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-USB Connector

The Micro-USB2 USB connector J9 provides an interface to access the FIFO/UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that FTDI USB driver is drivers are installed on your host PC.

JTAG Interface

JTAG access to the TEI0015 SoM through pin header connector J4. This is normally not needed as there is on-board USB JTAG functionality.

On-board Peripherals

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SDRAM

TEI0015 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

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FTDI FT2232H

The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity features of the FT2232H chip. FTDI FT2232H chip channel A is used in MPPSE mode for JTAG, 6 I/O's of . Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfacesis configured to be used in async FIFO mode, this is default mode when using preprogrammed FTDI configuration. In this mode the communication from host PC looks like normal UART but from the FTDI side it is 8 bit FIFO style interface.

The configuration of FTDI FT2232H chip is pre-programmed on in the EEPROM U9.

SPI Flash

SPI Flash

Optional SPI flash device maybe assembled in custom variants, normally it is not populatedOn-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interface.

EEPROM

The configuration of FTDI FT2232H chip is pre-programmed on in the EEPROM U9.

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Push Bottuns

Clock Sources

Power and Power-On Sequence

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

• Power on-sequence
• Power distribution
• Voltage monitoring circuit

Power and Power-On Sequence

Power Supply

The module is power supplied from USB (optionally via unpopulated pin header).

Power Consumption

Power Supply

To power-up the module, power supply with minimum current capability of 1A is recommended.

Power Consumption

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* TBD - To Be Determined

Actual power consumption depends on the FPGA design and ambient temperature.

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Power-On Sequence

There is no specific or special power-on sequence, just one single power source is needed. After power on the Green LED (D1) will be on.

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* TBD - To Be Determined

Actual power consumption depends on the FPGA design and ambient temperature.

Power Distribution Dependencies

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Power-On Sequence

There is no specific or special power-on sequence, just one single power source is needed. After power on the green LED (D1) will be on.

Power Rails