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        • type: Figure, Table
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          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
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      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

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  • Intel® MAX 10 Commercial [10M08SAU169C8G]

    • Package: UBGA-169

    • Speed Grade: C8 (Slowest)

    • Temperature: 0°C ~ to 85°C

    • Package compatible device 10M0210M08...10M16 as assembly variant on request possible

  • SDRAM Memory up to 64Mb, 166MHzDual High Speed USB to 32 Mbyte (8Mbyte default)

  • USB 2.0 Multipurpose UART/FIFO IC

  • 64 Mb Quad SPI Flash

  • (FT2232H)

    • 4 Kbit EEPROM Memory for FTDI configuration data
    • Micro USB Receptacle (communication and power)
  • SPI Flash - NOT INSTALLED (only special option)4Kb EEPROM Memory

  • 8x User LED Micro USB2 Receptacle 90
  • 18 Bit 2MSPS Analog to Digital Converter
  • 2x SMA Female Connector

  • I/O interface: 23x GPIO - Arduino MKR compatible

  • Power Supply: 5V

  • Minimum 1A

  • Dimension: 86.5mm x 25mm

  • Others:

    • Instrumentation Amplifier

    • Differential Amplifier

    • Operational Amplifier

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Scroll Title
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titleTEI0015 block diagram


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Main Components

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titleTEI0015 main components


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  1. SMA Connector, J5...6

  2. Amplifier, U12 - U14 - U6

  3. Series Voltage Reference, U8

  4. Analog to Digital ConvertorConverter, U15

  5. Voltage Regulator, U10 - U13 - U16

  6. Switching Voltage Regulator/LDO, U11 - U4

  7. SDRAM Memory, U2

  8. Intel® MAX 10 FPGA, U1
  9. Active serial SPI Flash Memory, U5

  10. 12.00 MHz MEMS oscillator, U7

  11. FTDI USB2 to JTAG/UART adapter, U3

  12. User LEDs, D2...9

  13. 4Kb FTDI configuration EEPROM, U9

  14. Configuration/Status LED (Red) , D10

  15. Power-on LED (Green), D1

  16. Push button, S1...2

  17. Micro USB2 ReceptacleUSB Connector, J9

  18. 1x14 pin header header, J2 (Not assembled), J2

  19. 1x6 pin header header, J4 (Not assembled), J4

  20. Jumper1x4 Header, J3 1x14 pin header  (Not assembled)

  21. 1x14 pin header, J1 (Not assembled)

Initial Delivery State

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Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

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Scroll Title
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titleInitial delivery state of programmable devices on the module

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SDRAM

Storage device name

Content

Notes

Quad SPI Flash

N/A

Not

Programmed

populated

EEPROM

Programmed

FTDI configuration

Not Programmed


Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.

The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or (using a *.POF file) on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile configuration memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up. To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile (using a *.SOF file), means the configuration is lost after power off.

Reset process must be done FPGA Reconfigration can be triggered by pressing push button S1.

Scroll Title
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titleReset process.

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Signal

Push ButtonPin HeaderNote

RESET

S1J2connected Connected to nCONFIG


Signals, Interfaces and Pins

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titleGeneral I/Os to Pin Headers and connectors information

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FPGA BankConnector DesignatorI/O Signal CountVoltage LevelNotes
Bank 1AJ173.3VAIN0...6
Bank 1BJ453.3VJTAG interface
Bank 2J143.3VDIO2...5
Bank 5J293.3VDIO6...14
J123.3VDIO0...1
Bank 8J213.3VRESET


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Scroll Title
anchorTable_OBP_IOs
titleFPGA I/O Banks


FPGA BankI/O Signal CountConnected toNotes
Bank 1A71x14 Pin header, J1AIN0...6
1Jumper, J3AIN7
Bank 1B51x6 Pin header, J4JTAG_EN, TDI, TDO, TMS, TCK
Bank 2


41x14 Pin header, J1D2...5
5A2D, U15ADC_EN, ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV
112MHz Oscillator, U7CLK12M
2Amplifier, U12nIAMP_A0, nIAMP_A1
Bank 322SDRAM, U2RAM_ADDR_CMD
Bank 59

1x14 Pin header, J2

DIO6...14
21x14 Pin header, J1DIO0...1
1D12_RDIO12
Bank 616SDRAM, U2DQ0...15
2SDRAM, U2DQM0...1
1D11_RDIO11
Bank 8



8User Red LEDs, D2...9LED0...7
6SPI Flash, U5F_CS, F_CKL, F_DI, F_DO, nSTATUS, DEVCLRn
1Red LED, D10CONF_DONE
6FTDI JTAG/UART Adapter, U3BDBUS0...5
1Push Button, S2USER_BTN


Micro

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-USB Connector

The Micro-USB2 USB connector J9 provides an interface to access the FIFO/UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that FTDI USB driver is drivers are installed on your host PC.

Scroll Title
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titleMicro USB-2 connector pins

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It is connected to GND
PinsConnected toNote
VBUSUSB_VBUS
D+

FTDI FT2232H U3, DP pin


D-

FTDI FT2232H U3, DM pin



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JTAG access to the TEI0015 SoM through pin header connector J4. This is normally not needed as there is on-board USB JTAG functionality.

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titleJTAG pins connection

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JTAG Signal

Pin Header Connector

Note
TMSJ4-6
TDIJ4-5
TDOJ4-4
TCK

J4-3


JTAG_ENJ4-2Connected Pulled-up to 3.3V


On-board Peripherals

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Scroll Title
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titleOn board peripherals

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Chip/InterfaceDesignatorNotes
SDRAM77530153U2
FTDI FT2232HU3JTAG/UART Adapter/FIFO
SPI FlashU5
EEPROM77530153U9
OscillatorU712MHz 12 MHz clock source
ADC77530153U12, U14Analog to Digital Converter
Push ButtonsS1...2
8x User LEDsD2...9Red LEDs


SDRAM

TEI0015 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

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Scroll Title
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titleSDRAM interface IOs and pins

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SDRAM I/O Signals

Signal Schematic Name

Connected toNotes
Address inputs

A0 ... A13

bank 3-
Bank address inputs

BA0 / BA1

bank 3

-
Data input/output

DQ0 ... DQ15

bank 6

-
Data mask

DQM0 ... DQM1

bank 6

-
ClockCLKbank 3-
Control Signals

CS

bank 3

Chip select

CKE

bank 3

Clock enable

RAS

bank 3

Row Address Strobe

CAS

bank 3

Column Address Strobe

WEbank 3Write Enable


FTDI FT2232H

The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity features of the FT2232H chip. FTDI FT2232H chip channel A is used in MPPSE mode for JTAG, 6 I/O's of . Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfacesis configured to be used in async FIFO mode, this is default mode when using preprogrammed FTDI configuration. In this mode the communication from host PC looks like normal UART but from the FTDI side it is 8 bit FIFO style interface.

The configuration of FTDI FT2232H chip is pre-programmed on in the EEPROM U9.

Scroll Title
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titleFTDI chip interfaces and pins

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FTDI Chip U3 PinSignal Schematic NameConnected toNotes
ADBUS0TCKFPGA bank 1B, pin G2JTAG interface
ADBUS1TDIFPGA bank 1B, pin F5
ADBUS2TDOFPGA bank 1B, pin F6
ADBUS3TMS

FPGA bank 1B, pin G1

BDBUS0BDBUS0FPGA bank 8, pin A4user User configurable
BDBUS1BDBUS1FPGA bank 8, pin B4user User configurable
BDBUS2BDBUS2FPGA bank 8, pin B5user User configurable
BDBUS3BDBUS3FPGA bank 8, pin A6user User configurable
BDBUS4BDBUS4FPGA bank 8, pin B6user User configurable
BDBUS5BDBUS5FPGA bank 8, pin A7user User configurable
BDBUS6

SPI Flash

BDBUS6FPGA bank 6, pin C11
BDBUS7BDBUS7FPGA bank 3, pin J7
BCBUS0BCBUS0FPGA bank 5, pin J9
BCBUS1BCBUS1FPGA bank 3, pin K5
BCBUS2BCBUS2FPGA bank 3, pin L4
BCBUS3BCBUS3FPGA bank 3, pin L5
BCBUS4BCBUS4FPGA bank 3, pin N12


SPI Flash

Optional SPI flash device maybe assembled in custom variants, normally it is not populatedOn-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interface.

Scroll Title
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titleQuad SPI Flash memory interface

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Signal Schematic NameConnected toNotes
F_CSFPGA bank 8, pin B3chip Chip select
F_CLKFPGA bank 8, pin A3clockClock
F_DIFPGA bank 8, pin A2data Data in / out
nSTATUS

FPGA bank 8, pin C4

data Data in / out, configuration dual-purpose pin of FPGA
DEVCLRNFPGA bank 8, pin B9data Data in / out, configuration dual-purpose pin of FPGA
F_DOFPGA bank 8, pin B2data Data in / out


EEPROM

The configuration of FTDI FT2232H chip is pre-programmed on in the EEPROM U9.

Scroll Title
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titleI2C EEPROM interface MIOs and pins

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SchematicConnected toNotes

EECS

FTDI U3, Pin EECS
EECLKFTDI U3, Pin EECLK
EEDATAFTDI U3, Pin EEDATA


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Scroll Title
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titleA2D converter interface and pins

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PinsConnected toNotes

IN+

Diff Amplifier U14, VOUT-
IN-Diff Amplifier U14, VOUT+
SDIFPGA, bank 2, pin M2, ADC_SDI
SDOFPGA, bank 2, pin M1,  ADC_SDO
SCKFPGA, bank 2, pin N3,  ADC_SCK
CNVFPGA, bank 2, pin N2, ADC_CNV


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Scroll Title
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titleOn-board LEDs

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DesignatorColorConnected toActive LevelNote
D2...9RedLED1...8Active HighUser LEDs
D10RedCONF_DONEActive LowConfiguration DONE LED
D1Green3.3V Active HighAfter power on it will be on.


Push Bottuns

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titleOn-board Push Buttons

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DesignatorConnected toFunctionalityNote
S1RESETGeneral reset
S2USER_BTNUser push buttonConnected to FPGA Bank 8.


Clock Sources

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titleOsillators

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Clock SourceSchematic NameFrequencyNote
Microchip MEMS Oscillator, U7CLK12M12.00 MHz

Connected to FTDI FT2232 U3, pin 3

Connected to FPGA SoC bank 2, pin H6

Power and Power-On Sequence

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hiddentrue
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit
Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

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Clock SourceSchematic NameFrequencyNote
MEMS Oscillator, U7CLK12M12.00 MHz

Connected to FTDI FT2232 U3, pin 3.

Connected to FPGA SoC bank 2, pin H6.


Power and Power-On Sequence

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

The module is power supplied from USB (optionally via unpopulated pin header).

Power Consumption

Power Supply

To power-up the module, power supply with minimum current capability of 1A is recommended.

Power Consumption

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anchorTable_PWR_PC
titlePower Consumption

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* TBD - To Be Determined

Actual power consumption depends on the FPGA design and ambient temperature.

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Power-On Sequence

There is no specific or special power-on sequence, just one single power source is needed. After power on the Green LED (D1) will be on.

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Typical Current
Intel MAX 10 10M08 FPGATBD*


* TBD - To Be Determined

Actual power consumption depends on the FPGA design and ambient temperature.

Power Distribution Dependencies

J2
Scroll Title
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titleModule power rails.Power Distribution


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Connector DesignatorVCC / VCCIO Schematic Name

Voltage

DirectionNotes
VIN5VInput3.3V3.3VOutput5V5VOutput

J9

USB_VBUS5VInput

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Power-On Sequence

There is no specific or special power-on sequence, just one single power source is needed. After power on the green LED (D1) will be on.

Power Rails

VCCIO2
Scroll Title
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titleIntel MAX 10 SoC bank voltagesModule power rails.

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Power Rail Name

Connector

J2 Pin

Connector

J9 Pin

DirectionNotes
VINJ2-13-Input5 V - Pin Header

Bank          

Schematic Name

Voltage

Notes
Bank 1AVCCIO1A3.3VBank 1B

VCCIO1B

3.3VBank 2
3.3V
Bank 3VCCIO33.3VBank 5VCCIO53.3VBank 6VCCIO63.3VBank 8VCCIO83.3V

Technical Specifications

Absolute Maximum Ratings

J2-12-Output
5VJ2-14-Output

USB_VBUS

-J9-1Input5 V - USB Connector


Bank Voltages

Scroll Title
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titleAbsolute maximum ratingsIntel MAX 10 SoC bank voltages.

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Bank          

Schematic Name

Voltage

Notes
Bank 1AVCCIO1A3.3V
Bank 1B

VCCIO1B

3.3V
Bank 2VCCIO23.3V
Bank 3VCCIO33.3V
Bank 5VCCIO53.3V
Bank 6VCCIO63.3V


Bank 8VCCIO83.3V



Technical Specifications

Absolute Maximum Ratings

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titleAbsolute maximum ratings

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CH1-25
SymbolsDescriptionMinMaxUnitReference Document

VIN 

Supply voltage4.755.25V
CH1-, CH1+
SymbolsDescriptionMinMaxUnitReference Document

VIN 

Supply voltage4.755.25V
VCC_ONESupply voltage for core and periphery through on-die voltage
regulator
-0.53.9VIntel MAX 10 datasheet
VCCIO

Supply voltage for input and output bufferse

-0.53.9VIntel MAX 10 datasheet
VCCASupply voltage for phase-locked loop (PLL) regulator and ADC-0.53.9VIntel MAX 10 datasheet
V_AN_INAnalog Input Voltage on ADC IC U15 pins–0.35.4VAD4003BCPZ datasheet
V_REFAnalog reference voltage on IC U15-0.36VAD4003BCPZ datasheet
CH1+Analog input voltage on amplifier U12 pin 1025VAD8251ARMZ datasheetAnalog input voltage on amplifier U12 pin 1, 10-3030VAD8251ARMZ AD8251 datasheet

T_STG

Storage Temperature-25+85°C


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see AD4003BCPZ
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titleRecommended operating conditions.

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SymbolsMinMaxUnitReference Document

VIN supply voltage (5.0V nominal)

4.755.25V
Analog input voltage on amplifier U12 pin 1 (CH1-), 10 (CH1+)-1010VAD8251
SymbolsMinMaxUnitReference Document

VIN supply voltage (5.0V nominal)

4.755.25V
VCC_ONE3.1353.456Vsee Intel MAX 10 datasheet
VCCIO3.1353.456Vsee Intel MAX 10 datasheet
VCCA3.1353.456Vsee Intel MAX 10 datasheet
V_AN_IN-0.15.1Vsee AD4003BCPZ datasheet
V_REF2.45.1V
datasheet

T_OP

0+70°CW9864G6JT-6 datasheet


Physical Dimensions

Module size: 25 mm × 86.5 mm.  Please download the assembly diagram for exact numbers.

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titlePhysical Dimension


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Scroll Title
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titleTrenz Electronic Shop Overview

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Trenz shop TEI0015 overview page
English pageGerman page


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titleHardware Revision History

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DateRevisionChangesDocumentation Link
2019-02-1101-REV01


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titleBoard hardware revision number.


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DateRevisionContributorDescription

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change list

  • multiple sections updated

2020-02-04

v.98ED
  • Technical Specifications updated

  • Power Rails updated

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