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Comment: Reverted from v. 96

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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:

        Scroll Title
        anchorFigure_anchorname
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • Scroll Title
        anchorTable_tablename
        titleText

        Scroll Table Layout
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        cellHighlightingtrue

        ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>


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Scroll Title
anchorFigure_OV_BD
titleTEI0015 block diagram


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Main Components

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Scroll Title
anchorFigure_OV_BD
titleTEI0015 main components


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  1. SMA Connector, J5...6

  2. Amplifier, U12 - U14 - U6

  3. Series Voltage Reference, U8

  4. Analog to Digital Converter, U15

  5. Voltage Regulator, U10 - U13 - U16

  6. Switching Voltage Regulator, U11 - U4

  7. SDRAM Memory, U2

  8. Intel® MAX 10, U1
  9. SPI Flash Memory, U5

  10. 12.00 MHz MEMS oscillator, U7

  11. FTDI USB2 to JTAG/UART adapter, U3

  12. User LEDs, D2...9

  13. FTDI configuration EEPROM, U9

  14. Configuration/Status LED (Red) , D10

  15. Power-on LED (Green), D1

  16. Push button, S1...2

  17. Micro USB Connector, J9

  18. 1x14 pin header, J2 (Not assembled)

  19. 1x6 pin header, J4 (Not assembled)

  20. 1x4 Header, J3 (Not assembled)

  21. 1x14 pin header, J1 (Not assembled)

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Scroll Title
anchorTable_OV_IDS
titleInitial delivery state of programmable devices on the module

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Storage device name

Content

Notes

Quad SPI Flash

Not Programmed


EEPROM

Programmed

FTDI configuration

SDRAMNot Programmed



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Scroll Title
anchorTable_OV_RST
titleReset process.

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Signal

Push ButtonPin HeaderNote

RESET

S1J2Connected to nCONFIG


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Scroll Title
anchorTable_SIP_GIOs
titleGeneral I/Os to Pin Headers and connectors information

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FPGA BankConnector DesignatorI/O Signal CountVoltage LevelNotes
Bank 1AJ173.3VAIN0...6
Bank 1BJ453.3VJTAG interface
Bank 2J143.3VDIO2...5
Bank 5J293.3VDIO6...14
J123.3VDIO0...1
Bank 8J213.3VRESET


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Scroll Title
anchorTable_OBP_USB
titleMicro USB-2 connector pins

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PinsConnected toNote
VBUSUSB_VBUS
D+

FTDI FT2232H U3, DP pin


D-

FTDI FT2232H U3, DM pin



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Scroll Title
anchorTable_SIP_JTG
titleJTAG pins connection

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JTAG Signal

Pin Header Connector

Note
TMSJ4-6
TDIJ4-5
TDOJ4-4
TCK

J4-3


JTAG_ENJ4-2Pulled-up to 3.3V


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Scroll Title
anchorTable_OBP
titleOn board peripherals

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Chip/InterfaceDesignatorNotes
SDRAMU2
FTDI FT2232HU3JTAG/UART Adapter
SPI FlashU5
EEPROMU9
OscillatorU712 MHz clock source
ADCU12, U14Analog to Digital Converter
Push ButtonsS1...2
8x User LEDsD2...9Red LEDs


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Scroll Title
anchorTable_OBP_SDRAM
titleSDRAM interface IOs and pins

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SDRAM I/O Signals

Signal Schematic Name

Connected toNotes
Address inputs

A0 ... A13

bank 3-
Bank address inputs

BA0 / BA1

bank 3

-
Data input/output

DQ0 ... DQ15

bank 6

-
Data mask

DQM0 ... DQM1

bank 6

-
ClockCLKbank 3-
Control Signals

CS

bank 3

Chip select

CKE

bank 3

Clock enable

RAS

bank 3

Row Address Strobe

CAS

bank 3

Column Address Strobe

WEbank 3Write Enable


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Scroll Title
anchorTable_OBP_FTDI
titleFTDI chip interfaces and pins

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FTDI Chip U3 PinSignal Schematic NameConnected toNotes
ADBUS0TCKFPGA bank 1B, pin G2JTAG interface
ADBUS1TDIFPGA bank 1B, pin F5
ADBUS2TDOFPGA bank 1B, pin F6
ADBUS3TMS

FPGA bank 1B, pin G1

BDBUS0BDBUS0FPGA bank 8, pin A4User configurable
BDBUS1BDBUS1FPGA bank 8, pin B4User configurable
BDBUS2BDBUS2FPGA bank 8, pin B5User configurable
BDBUS3BDBUS3FPGA bank 8, pin A6User configurable
BDBUS4BDBUS4FPGA bank 8, pin B6User configurable
BDBUS5BDBUS5FPGA bank 8, pin A7User configurable


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Scroll Title
anchorTable_OBP_QSPI
titleQuad SPI Flash memory interface

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Signal Schematic NameConnected toNotes
F_CSFPGA bank 8, pin B3Chip select
F_CLKFPGA bank 8, pin A3Clock
F_DIFPGA bank 8, pin A2Data in / out
nSTATUS

FPGA bank 8, pin C4

Data in / out, configuration dual-purpose pin of FPGA
DEVCLRNFPGA bank 8, pin B9Data in / out, configuration dual-purpose pin of FPGA
F_DOFPGA bank 8, pin B2Data in / out


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Scroll Title
anchorTable_OBP_EEP
titleI2C EEPROM interface MIOs and pins

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SchematicConnected toNotes

EECS

FTDI U3, Pin EECS
EECLKFTDI U3, Pin EECLK
EEDATAFTDI U3, Pin EEDATA


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Scroll Title
anchorTable_OBP_A2D
titleA2D converter interface and pins

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PinsConnected toNotes

IN+

Diff Amplifier U14, VOUT-
IN-Diff Amplifier U14, VOUT+
SDIFPGA, bank 2, pin M2, ADC_SDI
SDOFPGA, bank 2, pin M1,  ADC_SDO
SCKFPGA, bank 2, pin N3,  ADC_SCK
CNVFPGA, bank 2, pin N2, ADC_CNV


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Scroll Title
anchorTable_OBP_LED
titleOn-board LEDs

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DesignatorColorConnected toActive LevelNote
D2...9RedLED1...8Active HighUser LEDs
D10RedCONF_DONEActive LowConfiguration DONE LED
D1Green3.3V Active HighAfter power on it will be on.


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Scroll Title
anchorTable_OBP_LED
titleOn-board Push Buttons

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DesignatorConnected toFunctionalityNote
S1RESETGeneral reset
S2USER_BTNUser push buttonConnected to FPGA Bank 8.


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Scroll Title
anchorTable_OBP_CLK
titleOsillators

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Clock SourceSchematic NameFrequencyNote
Microchip MEMS Oscillator, U7CLK12M12.00 MHz

Connected to FTDI FT2232 U3, pin 3.

Connected to FPGA SoC bank 2, pin H6.


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Scroll Title
anchorTable_PWR_PC
titlePower Consumption

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FPGATypical Current
Intel MAX 10 10M08 FPGA SoCTBD*


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Scroll Title
anchorFigure_PWR_PD
titlePower Distribution


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Power-On Sequence

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Scroll Title
anchorTable_PWR_PR
titleModule power rails.

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Power Rail Name

Connector

J2 Pin

Connector

J9 Pin

DirectionNotes
VINJ2-13-Input5 V - Pin Header
3.3VJ2-12-Output
5VJ2-14-Output

USB_VBUS

-J9-1Input5 V - USB Connector


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Scroll Title
anchorTable_PWR_BV
titleIntel MAX 10 SoC bank voltages.

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Bank          

Schematic Name

Voltage

Notes
Bank 1AVCCIO1A3.3V
Bank 1B

VCCIO1B

3.3V
Bank 2VCCIO23.3V
Bank 3VCCIO33.3V
Bank 5VCCIO53.3V
Bank 6VCCIO63.3V


Bank 8VCCIO83.3V



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Scroll Title
anchorTable_TS_AMR
titleAbsolute maximum ratings

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SymbolsDescriptionMinMaxUnitReference Document

VIN 

Supply voltage4.755.25V
CH1-, CH1+Analog input voltage on amplifier U12 pin 1, 10-3030VAD8251 datasheet

T_STG

Storage Temperature-25+85°C


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Scroll Title
anchorTable_TS_ROC
titleRecommended operating conditions.

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SymbolsMinMaxUnitReference Document

VIN supply voltage (5.0V nominal)

4.755.25V
Analog input voltage on amplifier U12 pin 1 (CH1-), 10 (CH1+)-1010VAD8251 datasheet

T_OP

0+70°CW9864G6JT-6 datasheet


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Scroll Title
anchorFigure_TS_PD
titlePhysical Dimension


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Scroll Title
anchorTable_VCP_SO
titleTrenz Electronic Shop Overview

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Trenz shop TEI0023 TEI0015 overview page
English pageGerman page


Revision History

Hardware Revision History

Scroll Title
anchorTable_RH_HRH
titleHardware Revision History

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DateRevisionChangesDocumentation Link
20202019-0102-311101-REV01


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Scroll Title
anchorFigure_RV_HRN
titleBoard hardware revision number.


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Scroll Title
anchorTable_RH_DCH
titleDocument change history.

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DateRevisionContributorDescription

Page info
infoTypeModified date
dateFormatyyyy-MM-dd
typeFlat

Page info
infoTypeCurrent version
prefixv.
typeFlat
showVersionsfalse

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infoTypeModified by
typeFlat
showVersionsfalse

  • Technical Specifications updated

  • Power Rails updated

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all

Page info
infoTypeModified users
typeFlat
showVersionsfalse

  • --


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