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The Trenz Electronic TEI0015 is an commercial-grade module based on Intel® , low cost and small size module integrated with Intel® MAX 10. Intel Intel MAX 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.
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| anchor | Figure_OV_BD |
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| title | TExxxx block diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 68 |
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| diagramName | TEI0015_OV_BD |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 641 |
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| Scroll Title |
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| anchor | Figure_OV_BD |
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| title | TEI0015 main components |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 56 |
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| diagramName | TEI0015_OV_MC |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 641 |
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- SMA Connector, J5...6
- Instrumentation Amplifier, U12- U14
- Series Voltage Reference, U8
- Analog to Digital Convertor, U15- U6
- Voltage Regulator, U10- U13- U16
- Buck Switching Regulator, U11- U4
- Intel® MAX 10, U1
- SDRAM Memory, U2
- SPI Flash Memory, U5
- USP to UART convertor, U3
- User LEDs, D2...9
- 4Kb EEPROM, U9
- Switch, S1...2
- USB port, J9
- Pin Holder (Not assembled), J1...4
Initial Delivery State
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Notes : Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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| Scroll Title |
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| anchor | Table_OV_IDS |
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| title | Initial delivery state of programmable devices on the module |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Storage device name | Content | Notes |
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Quad SPI Flash | Not Programmed |
| | I2C Configuration EEPROM | Not Programmed |
| | SDRAM | Not Programmed |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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| Scroll Title |
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| anchor | Table_OV_BP |
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| title | Boot process. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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MODE Signal State | Boot Mode |
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The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up.
To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile, means the configuration is lost after power off.
Reset process must be done by pressing push button S1.
| Scroll Title |
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| anchor | Table_OV_RST |
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| title | Reset process. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| B2B | I/O| Push Button | Pin Header | Note |
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RESET | S1 | J2 | connected to nCONFIG |
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Signals, Interfaces and Pins
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Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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I/Os
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on Pin Headers and Connectors
| Scroll Title |
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| anchor | Table_SIP_B2B |
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| title | General PL I/O to B2B connectors information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FPGA Bank | B2B Connector Designator | I/O Signal Count | Voltage Level | Notes |
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