Page History
...
Page properties | ||||
---|---|---|---|---|
| ||||
Template Revision 2.6 8 - on construction Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board" |
...
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
Excerpt |
---|
|
...
Scroll Title | |||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| |||||||||||||||||||||||||||||||||
|
...
Scroll Title | ||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||
|
Hardware
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
...
Scroll Title | ||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||
|
...
Page properties | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Notes :
|
...
Scroll Title | ||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||
|
...
Reference Design is available on:
Design Flow
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
...
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter to start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
- Create HDF XSA and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
- Create Linux (bl31.elf uboot.elf and image.ub) with exported HDFXSA
- HDF XSA is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
- HDF XSA is exported to "prebuilt\hardware\<short name>"
- Add Linux files (bl31.el, uboot.elf and image.ub) to prebuilt folder
- "prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
- Generate Programming Files with HSI/SDKVitis
- Run on Vivado TCL: TE::sw_run_hsivitis -all
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdkvitis
Note: See SDK Projects TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis
- Run on Vivado TCL: TE::sw_run_hsivitis -all
Launch
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
...
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
QSPI
Get prebuilt boot binaries
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
- Select Create and open delivery binary folder
Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated
QSPI
Optional for Boot.bin on QSPI Flash and Optional for Boot.bin on QSPI Flash and image.ub on SD.
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash _binfile -swapp u-boot
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
optional "TE::pr_program_flash _binfile -swapp hello_te0802" possible - Copy image.ub on SD-Card
- use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see <design_name>/prebuilt/readme_file_For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to QSPI-Boot and insered SD.
- Depends on Carrier, see carrier TRM.
...
- Copy image.ub, Boot.bin and init.sh(optional on /misc/sd) on SD-Card.
- use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
- or use
- For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
...
Code Block | ||||
---|---|---|---|---|
| ||||
set_property PACKAGE_PIN E3 [get_ports PWM_L] set_property PACKAGE_PIN F4 [get_ports PWM_R] set_property IOSTANDARD LVCMOS18 [get_ports PWM_*] #set_property PACKAGE_PIN T2 [ get_ports USER_BTN_DOWN ] #set_property PACKAGE_PIN U2 [ get_ports USER_BTN_UP ] #set_property PACKAGE_PIN U1 [ get_ports USER_BTN_RIGHT ] #set_property PACKAGE_PIN R1 [ get_ports USER_BTN_LEFT ] #set_property PACKAGE_PIN T1 [ get_ports USER_BTN_OK ] #set_property IOSTANDARD LVCMOS18 [ get_ports USER_BTN_* ] set_property PACKAGE_PIN P3 [get_ports {USER_SW[0]}] set_property PACKAGE_PIN P2 [get_ports {USER_SW[1]}] set_property PACKAGE_PIN M1 [get_ports {USER_SW[2]}] set_property PACKAGE_PIN L1 [get_ports {USER_SW[3]}] set_property PACKAGE_PIN K1 [get_ports {USER_SW[4]}] set_property PACKAGE_PIN J2 [get_ports {USER_SW[5]}] set_property PACKAGE_PIN M4 [get_ports {USER_SW[6]}] set_property PACKAGE_PIN M5 [get_ports {USER_SW[7]}] set_property IOSTANDARD LVCMOS18 [get_ports USER_SW*] set_property PACKAGE_PIN U2 [get_ports {USER_BTN_UP}] set_property PACKAGE_PIN U1 [get_ports {USER_BTN_RIGHT}] set_property PACKAGE_PIN T2 [get_ports {USER_BTN_DOWN}] set_property PACKAGE_PIN R1 [get_ports {USER_BTN_LEFT}] set_property PACKAGE_PIN T1 [get_ports {USER_BTN_OK}] set_property IOSTANDARD LVCMOS18 [get_ports USER_BTN*] set_property PACKAGE_PIN P1 [get_ports {LED[0]}] set_property PACKAGE_PIN N2 [get_ports {LED[1]}] set_property PACKAGE_PIN M2 [get_ports {LED[2]}] set_property PACKAGE_PIN L2 [get_ports {LED[3]}] set_property PACKAGE_PIN J1 [get_ports {LED[4]}] set_property PACKAGE_PIN H2 [get_ports {LED[5]}] set_property PACKAGE_PIN L4 [get_ports {LED[6]}] set_property PACKAGE_PIN L3 [get_ports {LED[7]}] set_property IOSTANDARD LVCMOS18 [get_ports LED*] set_property PACKAGE_PIN F2 [get_ports {VGA_R[0]}] set_property PACKAGE_PIN F1 [get_ports {VGA_R[1]}] set_property PACKAGE_PIN G2 [get_ports {VGA_R[2]}] set_property PACKAGE_PIN G1 [get_ports {VGA_R[3]}] set_property PACKAGE_PIN C2 [get_ports {VGA_G[0]}] set_property PACKAGE_PIN D2 [get_ports {VGA_G[1]}] set_property PACKAGE_PIN D1 [get_ports {VGA_G[2]}] set_property PACKAGE_PIN E1 [get_ports {VGA_G[3]}] set_property PACKAGE_PIN A3 [get_ports {VGA_B[0]}] set_property PACKAGE_PIN A2 [get_ports {VGA_B[1]}] set_property PACKAGE_PIN B2 [get_ports {VGA_B[2]}] set_property PACKAGE_PIN B1 [get_ports {VGA_B[3]}] set_property PACKAGE_PIN B7 [get_ports {VGA_VS[0]}] set_property PACKAGE_PIN A6 [get_ports {VGA_HS[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_B[3]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_B[2]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_B[1]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_B[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_G[3]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_G[2]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_G[1]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_G[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {VGA_HS[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_R[3]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_R[2]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_R[1]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_R[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {VGA_VS[0]}] set_property PACKAGE_PIN J3 [get_ports CLK_25MHZ] set_property IOSTANDARD LVCMOS18 [get_ports CLK_25MHZ] # SEG_C[0] = SEG_CA set_property PACKAGE_PIN E4 [get_ports {SEG_C[0]}] set_property PACKAGE_PIN D3 [get_ports {SEG_C[1]}] set_property PACKAGE_PIN N5 [get_ports {SEG_C[2]}] set_property PACKAGE_PIN P5 [get_ports {SEG_C[3]}] set_property PACKAGE_PIN N4 [get_ports {SEG_C[4]}] set_property PACKAGE_PIN C3 [get_ports {SEG_C[5]}] set_property PACKAGE_PIN N3 [get_ports {SEG_C[7]}] set_property PACKAGE_PIN R5 [get_ports {SEG_C[6]}] set_property IOSTANDARD LVCMOS18 [get_ports SEG_C*] set_property PACKAGE_PIN A8 [get_ports {SEG_AN[0]}] set_property PACKAGE_PIN A9 [get_ports {SEG_AN[1]}] set_property PACKAGE_PIN B9 [get_ports {SEG_AN[2]}] set_property PACKAGE_PIN A7 [get_ports {SEG_AN[3]}] set_property PACKAGE_PIN B6 [get_ports {SEG_AN[4]}] set_property IOSTANDARD LVCMOS33 [get_ports SEG_AN*] |
Software Design -
...
Vitis
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
For SDK project creation, follow instructions from:SDK Projects
Application
Page properties | ||||
---|---|---|---|---|
| ||||
---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2018.3 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2018.3 xilisf_v5_11
---------------------------------------------------------- Zynq Example: zynq_fsblTE modified 2018.3 FSBL General:
Module Specific:
zynq_fsbl_flashTE modified 2018.3 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 20182019.3 2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 20182019.3 2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820te0802Hello TE0820 TE0802 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin. |
Template location: ./sw_lib/sw_apps/
zynqmp_fsbl
TE modified 20182019.3 2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
...
zynqmp_fsbl_flash
TE modified 20182019.3 2 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
...
Xilinx default PMU firmware.
hello_te0802
Hello TE0802 is a Xilinx Hello World example as endless loop instead of one console output.
Software Design - PetaLinux
...
Start with petalinux-config -c u-boot
Changes:
- CONFIG_ENV_IS_NOWHERE=y
- CONFIG_ENV_IS_IN_SPI_FLASH is not set
Change platform-top.h:
- CONFIG_I2C_EEPROM=y
- CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
- CONFIG_SYS_I2C_EEPROM_ADDR=0x50
- CONFIG_SYS_I2C_EEPROM_BUS=1
- CONFIG_SYS_EEPROM_SIZE=256
- CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0
- CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1
- CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0
Change platform-top.h:
Code Block | ||
---|---|---|
| ||
Code Block | ||
| ||
Device Tree
Code Block | ||
---|---|---|
| ||
/include/ "system-conf.dtsi" / { chosen { xlnx,eeprom = &eeprom; };/include/ "system-conf.dtsi" / { }; #include <dt-bindings/gpio/gpio.h> /* SD */ &sdhci0 { disable-wp; no-1-8-v; }; /* USB */ &dwc3_0 { status = "okay"; dr_mode = "host"; //snps,usb3_lpm_capable; //snps,dis_u3_susphy_quirk; //snps,dis_u2_susphy_quirk; //phy-names = "usb2-phy","usb3-phy"; //phys = <&lane1 4 0 2 26000000>; //maximum-speed = "super-speed"; }; / { leds { compatible = "gpio-leds"; ndp_en { label = "ndp_en"; gpios = <&gpio 26 GPIO_ACTIVE_HIGH>; default-state = "on"; }; ssd_sleep { label = "ssd_sleep"; gpios = <&gpio 32 GPIO_ACTIVE_HIGH>; default-state = "on"; }; usb_reset { label = "usb_reset"; gpios = <&gpio 38 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; }; /* ETH PHY */ &gem3 { phy-handle = <&phy0>; phy0: phy0@1 { device_type = "ethernet-phy"; reg = <1>; }; }; /* QSPI */ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cellscells = <1>; }; }; /* I2C */ &i2c1 { eeprom: eeprom@50 { compatible = "atmel,24c08"; reg = <1><0x50>; }; }; |
Kernel
Start with petalinux-config -c kernel
...
CONFIG_CPU_IDLE is not set (only needed to fix JTAG Debug issue)
CONFIG_CPU_FREQ is not set (only needed to fix JTAG Debug issue)
- CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set (only needed to fix JTAG Debug issue)
- CONFIG_BLK_DEV_NVME=y
- # CONFIG_NVME_MULTIPATH is not set
- CONFIG_NVME_TARGET=y
- # CONFIG_NVME_TARGET_LOOP is not set
- # CONFIG_NVME_TARGET_FC is not set
- CONFIG_NVM=y
- CONFIG_NVM_PBLK=y
- CONFIG_EDACNVM_CORTEXPBLK_ARM64DEBUG=y
Rootfs
Start with petalinux-config -c rootfs
...
Scroll Title | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
...