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Table of Contents

Table of Contents

Overview

The Trenz Electronic TE0xxx-xx ... is an industrial-grade ... module ... based on Xilinx ...TEP0006 is an Ultra96 LS Expansion to Pmod adapter.

Refer to http://trenz.org/tec0850tep0006-info for the current online version of this manual and other available documentation.

...

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Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features'  must be split into 6 main groups:

  • FPGA/Module
    • Package:
    • Speed:
    • Temperature:
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension
  • FPGAOn Board:
    • Package:
    • Speed:
    • Temperature:
  • RAM/Storage:
    • ...
    • ...
  • On Board:
    • ...
    • ...
  • Interface:
    • ...
    • ...
  • Power:
    • ...
    • ...
  • Dimension:
    • 4x Voltage Level Translators
    • 2x Voltage Regulators
  • Interface:
    • 1x Ultra96 LS Expansion Header (40 Pins)
    • 3x Pmod Connectors
    • 3x Jumpers
  • Power:
    • 5V
    • VCC_PSAUX
  • Dimension: 
    • 85 mm x 17 mm

Block Diagram

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Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


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Scroll Title
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titleTExxxx TEP0006 block diagram


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Main Components

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Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below
Note

For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .


...

Scroll Title
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titleTExxxx main componentsTEP0006 Main Components


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  1. ...
  2. ...
  3. ...

Initial Delivery State

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Notes :

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

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anchorTable_OV_IDS
titleInitial delivery state of programmable devices on the module
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  1. PMod 2x6 Host Socke (PMOD 2)  ,J2
  2. PMod 2x6 Host Socke (PMOD 2) ,J1
  3. Level Translator (HP_GPIO[0..7]) ,U1
  4. Level Translator (HP_GPIO[8..15]),U3
  5. Level Translator PMOD(SPI),U6
  6. Linear Voltage Regulator,U2
  7. Jumper,J6-J7
  8. PMod 2x6 Host Socke (SPI),J4
  9. GROVE,J5
  10. Level Translator (GROVE) ,U5
  11. Jumper (Voltage select ),J10
  12. Ultra96 LS Expansion Header (40 Pos),J3

Initial Delivery State

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Storage device name

...

Content

...

Notes

...

Quad SPI Flash

...

Configuration Signals

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Notes :

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

Overview of Boot Mode, Reset, Enables.


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titleBoot process.Initial delivery state of programmable devices on the module

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MODE Signal State

Boot Mode
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titleReset process.
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Signal

B2BI/ONote

Storage device name

Content

Notes

---------


Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.

Signals, Interfaces and Pins

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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

Low Speed Expansion Connector

The SMD Header J3 has 40 pin (20x2) and it is compatible with Ultra96 LS Expansion Connector. You can find General information about the LS Expansion connector in the following table.FPGA bank number and number of I/O signals connected to the B2B connector:

Scroll Title
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titleGeneral PL I/O to B2B connectors Ultra96 LS Expansion information

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FPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes

...

JTAG access to the TExxxx SoM through B2B connector JMX.

...

anchorTable_SIP_JTG
titleJTAG pins connection

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JTAG Signal

...

B2B Connector

...

MIO Pins

...

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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

SchematicConnected toNotes
HD_GPIO0...7Level Translator HP_GPIO[0...7], U1GPIO0...7

HD_GPIO8...15

Level Translator HP_GPIO[8...15], U3GPIO8...15

MIO36...37

Level Translator PMOD(SPI)PS_GPIO_0...1
MIO38, MIO41...43Level Translator PMOD(SPI)SPI
VCC_PSAUX

Level Translator, U1-U3-U5-U6

Voltage Regulator, U2

1.8 V

nPOK

5V

Voltage Regulator, U2

Jumper, J10

Vin

Pull up Voltage


Pmod Connectors

The TEP0006 is equipped with three Pmod connectors. Pmod Connectors are the expanded outputs from Ultra96 Board. 

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titlePmod Connectors information

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Pin

Connected to

Notes

Pmod 1, J1Pmod 2, J2 Pmod SPI, J4
1PMOD_HD-GPIO0PMOD_HD-GPIO8SS
2PMOD_HD-GPIO1PMOD_HD-GPIO9MOSI
3PMOD_HD-GPIO2PMOD_HD-GPIO10MISO
4PMOD_HD-GPIO3PMOD_HD-GPIO11SCK
5GNDGNDGND
63.3 V3.3 V3.3 V
7PMOD_HD-GPIO4PMOD_HD-GPIO12INIT
8PMOD_HD-GPIO5PMOD_HD-GPIO13RESET
9PMOD_HD-GPIO6PMOD_HD-GPIO14Not Connected
10PMOD_HD-GPIO7PMOD_HD-GPIO15Not Connected
11GNDGNDGND
123.3 V3.3 V3.3 V


Jumpers

...

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

...

anchorTable_OBP_MIOs
titleMIOs pins

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

...

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Notes :

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titleOn board peripheralsPmod Connectors information

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Chip/Interface
Designator
Notes

Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

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anchorTable_OBP_SPI
titleQuad SPI interface MIOs and pins

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anchorTable_OBP_RTC
titleI2C interface MIOs and pins

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anchorTable_OBP_I2C_RTC
titleI2C Address for RTC

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anchorTable_OBP_EEP
titleI2C EEPROM interface MIOs and pins

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anchorTable_OBP_I2C_EEPROM
titleI2C address for EEPROM

...

LEDs

...

anchorTable_OBP_LED
titleOn-board LEDs

...

DDR3 SDRAM

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Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

  • Part number: 
  • Supply voltage:
  • Speed: 
  • NOR Flash
  • Temperature: 

Ethernet

...

anchorTable_OBP_ETH
titleEthernet PHY to Zynq SoC connections

...

CAN Transceiver

...

anchorTable_OBP_CAN
titleCAN Tranciever interface MIOs

...

anchorTable_OBP_CLK
titleOsillators

...

Power and Power-On Sequence

...

hiddentrue
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit
Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

FunctionalityConnection BetweenNotes

J6

HD_GPIO_15

Level Translator U3 and U5

If you install the jumper HD_GPIO_15 will be driven through Level Translator (U5) and Grove (J5) otherwise it goes to Level Translator (U3).
J7HD_GPIO_11

Level Translator U3 and U5

If you put the jumper HD_GPIO_11 will be driven through Level Translator (U5) and Grove (J5) otherwise it goes to Level Translator (U3).
J10Voltage select

5 V, 3.3 V

Pull up Voltage



On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

Power Supply

Power supply with minimum current capability of xx A for system startup is recommended.

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titlePower ConsumptionOn board peripherals

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Power Input PinTypical Current
VINTBD*

* TBD - To Be Determined

Power Distribution Dependencies

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anchorFigure_PWR_PD
titlePower Distribution
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Chip/InterfaceDesignatorNotes
------


Power and Power-On Sequence

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power is supplied by Ultra96 Board through SMD Header J3.

Power Consumption

...

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titlePower SequencyConsumption

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Voltage Monitor Circuit

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titleVoltage Monitor Circuit
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Power Input PinTypical Current
5VTBD
VCC_PSAUXTBD


* TBD - To Be Determined

Power Distribution Dependencies

...

Scroll Title
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titleModule power rails.Power Distribution


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Power Rail Name

B2B Connector

JM1 Pin

B2B Connector

JM2 Pin

B2B Connector

JM3 Pin

DirectionNotes

...

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Power-On Sequence

There is no specific power on sequence, after power on the Ultra96 Board all electrical components on TEP0006 will be enabled.

Power Rails

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titleZynq SoC bank voltagesModule power rails.

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Bank          

Schematic Name

Voltage

Notes

...

hiddentrue
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...

use "include page" macro and link to the general B2B connector page of the module series,

...

? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.

3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)

true


Power Rail Name

LS Expansion Connector Pin

DirectionNotes
+5V37InputSupplied by Ultra96
VCC_PSAUX35InputSupplied by Ultra96

...


Technical Specifications

Absolute Maximum Ratings

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titlePS absolute maximum ratings

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SymbolsDescriptionMinMaxUnit
V
T_STGStorage Temperature-55150°C
VVVVVVV


Recommended Operating Conditions

...

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titleRecommended operating conditions.

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ParameterMinMaxUnitsReference Document
VSee ???? datasheets.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.°CSee Xilinx ???? datasheet.°CSee Xilinx ???? datasheet.
cellHighlightingtrue

ParameterMinMaxUnitsReference Document
T_OPT-40+85°C


Physical Dimensions

  • Module size: ?? 85 mm × ?? 17 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: ? mm.

PCB thickness: ?? 1.6 mm.

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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .



Scroll Title
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titlePhysical Dimension


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Currently Offered Variants 

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Set correct link to the shop page overview table of the product on English and German.

Example for TE0728:

    ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

    DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

For Baseboards or modules, where no overview page is available (and revision number is coded in the direct link) use shop search link, e.g. TE0706:

    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706TEP0006

   DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706

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titleTrenz Electronic Shop Overview

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Trenz shop TE0728 TEP0006 overview page
English pageGerman page


Revision History

Hardware Revision History

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titleHardware Revision History

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DateRevisionChangesDocumentation LinkRevisionChangesDocumentation Link
2019-07-1901Initial ReleaseREV01


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

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title
Board hardware revision number.


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titleBoard hardware revision number.
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Document Change History

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  • It's semi automatically, so do following

    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports

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DateRevisionContributorDescription|

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  • change listInitial release

--

all

Page info
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  • --


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