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Note for Download Link of the Scroll ignore macro:

Link to the base folder of the module (remove de/ or en/ from the URL):
Example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5_Carriers/TE0728/

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Download PDF version of this document.

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Table of Contents

Table of Contents

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The Trenz Electronic TEP0006 is a Pmod an Ultra96 LS Expansion to Pmod adapter.

Refer to http://trenz.org/tep0006-info for the current online version of this manual and other available documentation.

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Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features' must be split into 6 main groups:

FPGA/Module
- Package:
- Speed:
- Temperature:
RAM/Storage
- E.g. SDRAM, SPI
On Board
- E.g. CPLD, PLL
Interface
- E.g. ETH, USB, B2B, Display port
Power
- E.g. Input supply voltage
Dimension

On Board:
- 4x Voltage Level Translators
- 2x Voltag Voltage Regulators
- ...
Interface:
- 1x Ultra96 LS Expansion Header (40 Pins)
- .3x Pmod HeaderConnectors
- 3x Jumpers
Power:
- 5V
- VCC_PSAUX
Dimension:
- 85 mm x 17 mm

Block Diagram

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add drawIO object here.

Note
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .

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anchor	Figure_OV_BD
title	TEP0006 block diagram

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draw.io Diagram

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Main Components

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title	TEP0006 Main Components

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PMod 2x6 Host Socke (PMOD 2) ,J2
PMod 2x6 Host Socke (PMOD 2) ,J1
Level Translator (HP_GPIO[0..7]) ,U1
Level Translator (HP_GPIO[8..15]),U3
Level Translator PMOD(SPI),U6
Linear Voltage Regulator,U2
Jumper,J6-J7
PMod 2x6 Host Socke (SPI),J4
GROVE,J5
Level Translator (GROVE) ,U5
Jumper (Voltage select ),J10
SMD Header (Ultra96 LS Expansion Header (40 Pos),J3

Initial Delivery State

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Notes :

For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- SD
- USB
- ETH
- FMC
- ...
For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
- JTAG
- UART
- I2C
- MGT
- ...

Board to Board (B2B) I/Os

Low Speed Expansion Connector

The SMD Header J3 has 40 pin (20x2) and it is compatible with Ultra96 LS Expansion Connector. You can find General information about the LS Expansion connector in the following table.FPGA bank number and number of I/O signals connected to the B2B connector:

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anchor	Table_SIP_B2BUltra96
title	General PL I/O to B2B connectors Ultra96 LS Expansion information

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FPGA Bank

B2B Connector

I/O Signal Count

Voltage Level

Notes

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JTAG access to the TExxxx SoM through B2B connector JMX.

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anchor	Table_SIP_JTG
title	JTAG pins connection

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JTAG Signal

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B2B Connector

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MIO Pins

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id	Comments

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

Schematic	Connected to	Notes
HD_GPIO0...7	Level Translator HP_GPIO[0...7], U1	GPIO0...7
HD_GPIO8...15	Level Translator HP_GPIO[8...15], U3	GPIO8...15
MIO36...37	Level Translator PMOD(SPI)	PS_GPIO_0...1
MIO38, MIO41...43	Level Translator PMOD(SPI)	SPI
VCC_PSAUX	Level Translator, U1-U3-U5-U6 Voltage Regulator, U2	1.8 V nPOK
5V	Voltage Regulator, U2 Jumper, J10	Vin Pull up Voltage

Pmod Connectors

The TEP0006 is equipped with three Pmod connectors. Pmod Connectors are the expanded outputs from Ultra96 Board.

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title	Pmod Connectors information

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Pin	Connected to			Notes
Pin	Pmod 1, J1	Pmod 2, J2	Pmod SPI, J4	Notes
1	PMOD_HD-GPIO0	PMOD_HD-GPIO8	SS
2	PMOD_HD-GPIO1	PMOD_HD-GPIO9	MOSI
3	PMOD_HD-GPIO2	PMOD_HD-GPIO10	MISO
4	PMOD_HD-GPIO3	PMOD_HD-GPIO11	SCK
5	GND	GND	GND
6	3.3 V	3.3 V	3.3 V
7	PMOD_HD-GPIO4	PMOD_HD-GPIO12	INIT
8	PMOD_HD-GPIO5	PMOD_HD-GPIO13	RESET
9	PMOD_HD-GPIO6	PMOD_HD-GPIO14	Not Connected
10	PMOD_HD-GPIO7	PMOD_HD-GPIO15	Not Connected
11	GND	GND	GND
12	3.3 V	3.3 V	3.3 V

Jumpers

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anchor	Table_SIP_Pmod
title	Pmod Connectors information

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SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

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anchor	Table_OBP_MIOs
title	MIOs pins

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Notes :

add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs

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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

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anchor	Table_OBP
title	On board peripherals

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Chip/Interface

Designator

Notes

Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

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anchor	Table_OBP_SPI
title	Quad SPI interface MIOs and pins

Functionality	Connection Between	Notes
J6	HD_GPIO_15	Level Translator U3 and U5	If you install the jumper HD_GPIO_15 will be driven through Level Translator (U5) and Grove (J5) otherwise it goes to Level Translator (U3).
J7	HD_GPIO_11	Level Translator U3 and U5	If you put the jumper HD_GPIO_11 will be driven through Level Translator (U5) and Grove (J5) otherwise it goes to Level Translator (U3).
J10	Voltage select	5 V, 3.3 V	Pull up Voltage

On-board Peripherals

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Notes :

add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs

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hidden	true
id	Comments

Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

Scroll Title

anchor	Table_OBP
title	On board peripherals

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orientation

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anchor	Table_OBP_RTC
title	I2C interface MIOs and pins

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MIO Pin

Schematic

U? Pin

Notes

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anchor	Table_OBP_I2C_RTC
title	I2C Address for RTC

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MIO Pin

I2C Address

Designator

Notes

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Chip/Interface	Designator	Notes
--	--	--

Power and Power-On Sequence

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

Power on-sequence
Power distribution
Voltage monitoring circuit

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Power Supply

Power is supplied by Ultra96 Board through SMD Header J3.

Power Consumption

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title	I2C EEPROM interface MIOs and pinsPower Consumption

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Notes

MIO Power Input Pin	Typical Current	Schematic	U?? Pin
5V	TBD
VCC_PSAUX	TBD

* TBD - To Be Determined

Power Distribution Dependencies

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anchor	TableFigure_OBPPWR_I2C_EEPROMPD
title	I2C address for EEPROMPower Distribution

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MIO Pin

I2C Address

Designator

Notes

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diagramName	TEP0006_PWR_PD
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Power-On Sequence

There is no specific power on sequence, after power on the Ultra96 Board all electrical components on TEP0006 will be enabled.

Power Rails

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title	On-board LEDsModule power rails.

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Designator

Color

Connected to

Active Level

Note

DDR3 SDRAM

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Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

Part number:
Supply voltage:
Speed:
NOR Flash
Temperature:

Ethernet

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anchor	Table_OBP_ETH
title	Ethernet PHY to Zynq SoC connections

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CAN Transceiver

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anchor	Table_OBP_CAN
title	CAN Tranciever interface MIOs

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anchor	Table_OBP_CLK
title	Osillators

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Power and Power-On Sequence

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hidden	true
id	Comments

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

Power on-sequence
Power distribution
Voltage monitoring circuit

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Power Supply

Power supply with minimum current capability of xx A for system startup is recommended.

Power Consumption

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anchor	Table_PWR_PC
title	Power Consumption

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* TBD - To Be Determined

Power Distribution Dependencies

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anchor	Figure_PWR_PD
title	Power Distribution

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Power-On Sequence

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anchor	Figure_PWR_PS
title	Power Sequency

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Power Rails

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anchor	Table_PWR_PR
title	Module power rails.

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B2B Connector

JM1 Pin

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B2B Connector

JM2 Pin

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B2B Connector

JM3 Pin

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Bank Voltages

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anchor	Table_PWR_BV
title	Zynq SoC bank voltages.

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Bank

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Voltage

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hidden	true
id	Comments

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use "include page" macro and link to the general B2B connector page of the module series,

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? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.

3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)

Power Rail Name	LS Expansion Connector Pin	Direction	Notes
+5V	37	Input	Supplied by Ultra96
VCC_PSAUX	35	Input	Supplied by Ultra96

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Technical Specifications

Absolute Maximum Ratings

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title	PS absolute maximum ratings

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Symbols	Description	Min	Max	Unit

V

T_STG

Storage Temperature

-55

150

°C

Recommended Operating Conditions

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title	Recommended operating conditions.

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See Xilinx ???? datasheet.

Parameter	Min	Max	Units	Reference Document	V	See Xilinx ???? datasheet.	°C	See Xilinx ???? datasheet.	°C
T_OPT	-40	+85	°C

Physical Dimensions

Module size: ?? 85 mm × ?? 17 mm. Please download the assembly diagram for exact numbers.Mating height with standard connectors: ? mm.

PCB thickness: ?? 1.6 mm.

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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Figure

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anchor	Figure_TS_PD

Scroll Title

title	Physical Dimension

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draw.io Diagram

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title

Physical Dimension

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scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixedImage Added

Currently Offered Variants

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hidden	true
id	Comments

Set correct link to the shop page overview table of the product on English and German.

Example for TE0728:

ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

For Baseboards or modules, where no overview page is available (and revision number is coded in the direct link) use shop search link, e.g. TE0706:

ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706TEP0006

DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706

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title	Trenz Electronic Shop Overview

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Trenz shop TE0728 TEP0006 overview page
English page	German page

Revision History

Hardware Revision History

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Date	Revision	Changes	Documentation Link		Revision	Changes	Documentation Link
2019-07-19	01	Initial Release	REV01

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

scroll-title

title
anchor	Figure_RV_HRN

	Board hardware revision number.

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draw.io Diagram

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diagramName	TEP0006_RV_HRN
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diagramWidth	180

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anchor	Figure_RV_HRN
title	Board hardware revision number.

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Document Change History

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Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
- Add new row below first
- Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
- Metadata is only used of compatibility of older exports

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title	Document change history.

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Date

Revision

Contributor

Description|

Page info

infoType	Modified date
dateFormat	yyyy-MM-dd
type	Flat

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infoType	Current version
prefix	v.
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change listInitial release

--

all

Page info

infoType	Modified users
type	Flat
showVersions	false

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Trenz Electronic Documentation

Versions Compared

Old Version 3

New Version Current

Key

Block Diagram

Main Components

Initial Delivery State

Board to Board (B2B) I/Os

Low Speed Expansion Connector

MIO Pins

Pmod Connectors

Jumpers

Quad SPI Flash Memory

On-board Peripherals

Power and Power-On Sequence

Power Supply

Power Consumption

Power Distribution Dependencies

Power-On Sequence

Power Rails

DDR3 SDRAM

Ethernet

CAN Transceiver

Power and Power-On Sequence

Power Supply

Power Consumption

Power Distribution Dependencies

Power-On Sequence

Power Rails

Bank Voltages

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Physical Dimensions

Currently Offered Variants

Revision History

Hardware Revision History

Document Change History