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Table of Contents

Table of Contents

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The Trenz Electronic TEP0006 is a Pmod an Ultra96 LS Expansion to Pmod adapter.

Refer to http://trenz.org/tep0006-info for the current online version of this manual and other available documentation.

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Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features'  must be split into 6 main groups:

  • FPGA/Module
    • Package:
    • Speed:
    • Temperature:
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension
  • On Board:
    • 4x Voltage Level Translators
    • 2x Voltag Voltage Regulators
    • ...
  • Interface:
    • 1x Ultra96 LS Expansion Header (40 Pins)
    • .3x Pmod HeaderConnectors
    • 3x Jumpers
  • Power:
    • 5V
    • VCC_PSAUX
  • Dimension: 
    • 85 mm x 17 mm

Block Diagram

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For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


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Scroll Title
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titleTEP0006 block diagram


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draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
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lboxtrue
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diagramNameTEP0006_OV_BD
simpleViewerfalse
width
linksauto
tbstylehidden
diagramWidth641


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Main Components

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titleTEP0006 Main Components


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borderfalse
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simpleViewerfalse
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linksauto
tbstylehidden
diagramWidth641


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  1. PMod 2x6 Host Socke (PMOD 2)  ,J2
  2. PMod 2x6 Host Socke (PMOD 2) ,J1
  3. Level Translator (HP_GPIO[0..7]) ,U1
  4. Level Translator (HP_GPIO[8..15]),U3
  5. Level Translator PMOD(SPI),U6
  6. Linear Voltage Regulator,U2
  7. Jumper,J6-J7
  8. PMod 2x6 Host Socke (SPI),J4
  9. GROVE,J5
  10. Level Translator (GROVE) ,U5
  11. Jumper (Voltage select ),J10
  12. SMD Header (Ultra96 LS Expansion Header (40 Pos),J3

Initial Delivery State

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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

Low Speed Expansion Connector

The SMD Header J3 has 40 pin (20x2) and it is compatible with Ultra96 LS Expansion Connector. You can find General information about the LS Expansion connector in the following table.FPGA bank number and number of I/O signals connected to the B2B connector:

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titleGeneral PL I/O to B2B connectors Ultra96 LS Expansion information

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FPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes

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JTAG access to the TExxxx SoM through B2B connector JMX.

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anchorTable_SIP_JTG
titleJTAG pins connection

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JTAG Signal

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B2B Connector

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MIO Pins

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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

SchematicConnected toNotes
HD_GPIO0...7Level Translator HP_GPIO[0...7], U1GPIO0...7

HD_GPIO8...15

Level Translator HP_GPIO[8...15], U3GPIO8...15

MIO36...37

Level Translator PMOD(SPI)PS_GPIO_0...1
MIO38, MIO41...43Level Translator PMOD(SPI)SPI
VCC_PSAUX

Level Translator, U1-U3-U5-U6

Voltage Regulator, U2

1.8 V

nPOK

5V

Voltage Regulator, U2

Jumper, J10

Vin

Pull up Voltage


Pmod Connectors

The TEP0006 is equipped with three Pmod connectors. Pmod Connectors are the expanded outputs from Ultra96 Board. 

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titlePmod Connectors information

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Pin

Connected to

Notes

Pmod 1, J1Pmod 2, J2 Pmod SPI, J4
1PMOD_HD-GPIO0PMOD_HD-GPIO8SS
2PMOD_HD-GPIO1PMOD_HD-GPIO9MOSI
3PMOD_HD-GPIO2PMOD_HD-GPIO10MISO
4PMOD_HD-GPIO3PMOD_HD-GPIO11SCK
5GNDGNDGND
63.3 V3.3 V3.3 V
7PMOD_HD-GPIO4PMOD_HD-GPIO12INIT
8PMOD_HD-GPIO5PMOD_HD-GPIO13RESET
9PMOD_HD-GPIO6PMOD_HD-GPIO14Not Connected
10PMOD_HD-GPIO7PMOD_HD-GPIO15Not Connected
11GNDGNDGND
123.3 V3.3 V3.3 V


Jumpers

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SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

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anchorTable_OBP_MIOs
titleMIOs pins

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs
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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

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anchorTable_OBP
titleOn board peripherals

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Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

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anchorTable_OBP_SPI
titleQuad SPI interface MIOs and pins

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anchorTable_OBP_RTC
titleI2C interface MIOs and pins

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anchorTable_OBP_I2C_RTC
titleI2C Address for RTC

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anchorTable_OBP_EEP
titleI2C EEPROM interface MIOs and pins

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anchorTable_OBP_I2C_EEPROM
titleI2C address for EEPROM

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LEDs

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anchorTable_OBP_LED
titleOn-board LEDs

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DDR3 SDRAM

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Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

  • Part number: 
  • Supply voltage:
  • Speed: 
  • NOR Flash
  • Temperature: 

Ethernet

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anchorTable_OBP_ETH
titleEthernet PHY to Zynq SoC connections

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titleOsillatorsPmod Connectors information

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DesignatorDescriptionFrequencyNote

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DesignatorFunctionalityConnection BetweenNotes

J6

HD_GPIO_15

Level Translator U3 and U5

If you install the jumper HD_GPIO_15 will be driven through Level Translator (U5) and Grove (J5) otherwise it goes to Level Translator (U3).
J7HD_GPIO_11

Level Translator U3 and U5

If you put the jumper HD_GPIO_11 will be driven through Level Translator (U5) and Grove (J5) otherwise it goes to Level Translator (U3).
J10Voltage select

5 V, 3.3 V

Pull up Voltage



On-board Peripherals

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit
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Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Power Supply

Power supply with minimum current capability of xx A for system startup is recommended.

Power Consumption

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


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titlePower ConsumptionOn board peripherals

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Power Input PinTypical Current
VINTBD*

* TBD - To Be Determined

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Chip/InterfaceDesignatorNotes
------


Power and Power-On Sequence

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power is supplied by Ultra96 Board through SMD Header J3.

Power Consumption

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titlePower DistributionConsumption

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tablelayout

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viewerToolbar

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true

repeatTableHeaders

fitWindowfalse
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diagramNameTEP0006_PWR_PD
simpleViewerfalse
width
linksauto
tbstylehidden
diagramWidth641
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Power-On Sequence

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titlePower Sequency
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Power Input PinTypical Current
5VTBD
VCC_PSAUXTBD


* TBD - To Be Determined

Power Distribution Dependencies

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titleModule power rails.Power Distribution


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Power Rail Name

B2B Connector

JM1 Pin

B2B Connector

JM2 Pin

B2B Connector

JM3 Pin

DirectionNotes

Bank Voltages

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draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
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simpleViewerfalse
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linksauto
tbstylehidden
diagramWidth641


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Power-On Sequence

There is no specific power on sequence, after power on the Ultra96 Board all electrical components on TEP0006 will be enabled.

Power Rails


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titleZynq SoC bank voltagesModule power rails.

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Bank          

Schematic Name

Voltage

Notes
Power Rail Name

LS Expansion Connector Pin

DirectionNotes
+5V37InputSupplied by Ultra96
VCC_PSAUX35InputSupplied by Ultra96


Technical Specifications

Absolute Maximum Ratings

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titlePS absolute maximum ratings

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SymbolsDescriptionMinMaxUnitInput Supply VoltageV
T_STGStorage Temperature-55150°C


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titleRecommended operating conditions.

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See Xilinx ???? datasheet.
ParameterMinMaxUnitsReference DocumentVin55VReference Document
T_OPT-40+85°C


Physical Dimensions

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titlePhysical Dimension


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borderfalse
viewerToolbartrue
fitWindowfalse
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diagramNameTEP0006_TS_PD
simpleViewerfalse
width
linksauto
tbstylehidden
diagramWidth641


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scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue

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Currently Offered Variants 

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titleHardware Revision History

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DateRevisionChangesDocumentation Link
2019-07-19REV0101Initial ReleaseREV01


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

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titleBoard hardware revision number.


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borderfalse
viewerToolbartrue
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diagramNameTEP0006_RV_HRN
simpleViewerfalse
width
linksauto
tbstylehidden
diagramWidth188180


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Document Change History

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titleDocument change history.

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orientationportrait
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DateRevisionContributorDescription|

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infoTypeModified date
dateFormatyyyy-MM-dd
typeFlat

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infoTypeCurrent version
prefixv.
typeFlat
showVersionsfalse

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  • change listInitial release

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all

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