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Table of Contents |
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The Trenz Electronic TEP0006 is a Pmod an Ultra96 LS Expansion to Pmod adapter.
Refer to http://trenz.org/tep0006-info for the current online version of this manual and other available documentation.
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Note: 'description: Important components and connector or other Features of the module → please sort and indicate assembly options Key Features' must be split into 6 main groups: - FPGA/Module
- Package:
- Speed:
- Temperature:
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
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- On Board:
- 4x Voltage Level Translators
- 2x Voltag Voltage Regulators
- ...
- Interface:
- 1x Ultra96 LS Expansion Header (40 Pins)
- .3x Pmod HeaderConnectors
- 3x Jumpers
- Power:
- Dimension:
Block Diagram
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add drawIO object here.
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title | TEP0006 block diagram |
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Main Components
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title | TEP0006 Main Components |
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- PMod 2x6 Host Socke (PMOD 2) ,J2
- PMod 2x6 Host Socke (PMOD 2) ,J1
- Level Translator (HP_GPIO[0..7]) ,U1
- Level Translator (HP_GPIO[8..15]),U3
- Level Translator PMOD(SPI),U6
- Linear Voltage Regulator,U2
- Jumper,J6-J7
- PMod 2x6 Host Socke (SPI),J4
- GROVE,J5
- Level Translator (GROVE) ,U5
- Jumper (Voltage select ),J10
- SMD Header (Ultra96 LS Expansion Header (40 Pos),J3
Initial Delivery State
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Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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Low Speed Expansion Connector
The SMD Header J3 has 40 pin (20x2) and it is compatible with Ultra96 LS Expansion
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Connector. You can find General information about GPIO connection to the Ultra96 the LS Expansion connector :in the following table.
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anchor | Table_SIP_Ultra96 |
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title | Ultra96 LS Expansion information |
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orientation | portrait |
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Schematic | Connected to | Notes |
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HD_GPIO0...7 | Level Translator HP_GPIO[0...7], U1GPIO | GPIO0...7 | HD_GPIO8...15 | Level Translator HP_GPIO[8...15], U3 | GPIOGPIO8...15 | MIO36 -...37 | Level Translator PMOD(SPI)GPIO0-GPIO1 | PS_GPIO_0...1 | MIO38, MIO41...43 | Level Translator PMOD(SPI) | SPI | VCC_PSAUX | Level Translator, U1-U3-U5-U6 Voltage Regulator, U2 | 1.8 V nPOK | 5V | Voltage Regulator, U2 Jumper, J10 | Vin Pull up Voltage |
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Pmod Connectors
The TEP0006 is equipped with three Pmod connectors. Pmod Connectors are the expanded outputs from Ultra96 Board.
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anchor | Table_SIP_Pmod |
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title | Pmod Connectors information |
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orientation | portrait |
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SchematicHD_GPIO0...7 | Level Translator HP_GPIO[0...7], U1 | GPIO | HD_GPIO8...15 | Level Translator HP_GPIO[8...15], U3 | GPIO | MIO36-37 | Level Translator PMOD(SPI) | GPIO0-GPIO1 | MIO38, MIO41...43 | Level Translator PMOD(SPI) | SPI | VCC_PSAUX | Level Translator, U1-U3-U5-U6 Voltage Regulator, U2 | 1.8 V | 5V | Voltage Regulator, U2 Jumper, J10 | |
MIO Pins
Pmod 1, J1 | Pmod 2, J2 | Pmod SPI, J4 |
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1 | PMOD_HD-GPIO0 | PMOD_HD-GPIO8 | SS |
| 2 | PMOD_HD-GPIO1 | PMOD_HD-GPIO9 | MOSI |
| 3 | PMOD_HD-GPIO2 | PMOD_HD-GPIO10 | MISO |
| 4 | PMOD_HD-GPIO3 | PMOD_HD-GPIO11 | SCK |
| 5 | GND | GND | GND |
| 6 | 3.3 V | 3.3 V | 3.3 V |
| 7 | PMOD_HD-GPIO4 | PMOD_HD-GPIO12 | INIT |
| 8 | PMOD_HD-GPIO5 | PMOD_HD-GPIO13 | RESET |
| 9 | PMOD_HD-GPIO6 | PMOD_HD-GPIO14 | Not Connected |
| 10 | PMOD_HD-GPIO7 | PMOD_HD-GPIO15 | Not Connected |
| 11 | GND | GND | GND |
| 12 | 3.3 V | 3.3 V | 3.3 V |
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Jumpers
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anchor | Table_SIP_Pmod |
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title | Pmod Connectors information |
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.
Example:
MIO Pin | Connected to | B2B | Notes |
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MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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anchor | Table_OBP_MIOs |
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title | MIOs pins |
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orientation | portrait |
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
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anchor | Table_OBP |
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title | On board peripherals |
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Quad SPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
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anchor | Table_OBP_SPI |
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title | Quad SPI interface MIOs and pins |
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anchor | Table_OBP_RTC |
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title | I2C interface MIOs and pins |
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anchor | Table_OBP_I2C_RTC |
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title | I2C Address for RTC |
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anchor | Table_OBP_EEP |
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title | I2C EEPROM interface MIOs and pins |
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anchor | Table_OBP_I2C_EEPROM |
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title | I2C address for EEPROM |
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LEDs
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anchor | Table_OBP_LED |
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title | On-board LEDs |
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DDR3 SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.
- Part number:
- Supply voltage:
- Speed:
- NOR Flash
- Temperature:
Ethernet
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anchor | Table_OBP_ETH |
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title | Ethernet PHY to Zynq SoC connections |
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Clock Sources
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anchor | Table_OBP_CLK |
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title | Osillators |
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Power and Power-On Sequence
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
- Power on-sequence
- Power distribution
- Voltage monitoring circuit
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For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" . |
J6 | HD_GPIO_15 | Level Translator U3 and U5 | If you install the jumper HD_GPIO_15 will be driven through Level Translator (U5) and Grove (J5) otherwise it goes to Level Translator (U3). | J7 | HD_GPIO_11 | Level Translator U3 and U5 | If you put the jumper HD_GPIO_11 will be driven through Level Translator (U5) and Grove (J5) otherwise it goes to Level Translator (U3). | J10 | Voltage select | 5 V, 3.3 V | Pull up Voltage |
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On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
Power Supply
Power supply with minimum current capability of xx A for system startup is recommended.
Power Consumption
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anchor | Table_PWR_PCOBP |
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title | Power ConsumptionOn board peripherals |
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Power Input Pin | Typical Current |
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VIN | TBD* |
* TBD - To Be Determined
Power Distribution Dependencies
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anchor | Figure_PWR_PD |
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title | Power Distribution |
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Chip/Interface | Designator | Notes |
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-- | -- | -- |
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Power and Power-On Sequence
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
Power is supplied by Ultra96 Board through SMD Header J3.
Power Consumption
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title | Power SequencyConsumption |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Power Input Pin | Typical Current |
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5V | TBD | VCC_PSAUX | TBD |
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* TBD - To Be Determined
Power Distribution Dependencies
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anchor | TableFigure_PWR_PRPD |
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title | Module power rails.Power Distribution |
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Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
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Power-On Sequence
There is no specific power on sequence, after power on the Ultra96 Board all electrical components on TEP0006 will be enabled.
Power Rails
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anchor | Table_PWR_BVPR |
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title | Zynq SoC bank voltagesModule power rails. |
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Power Rail Name | LS Expansion Connector Pin | Direction | Notes |
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+5V | 37 | Input | Supplied by Ultra96 | VCC_PSAUX | 35 | Input | Supplied by Ultra96 |
| Schematic Name | | Notes
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Technical Specifications
Absolute Maximum Ratings
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anchor | Table_TS_AMR |
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title | PS absolute maximum ratings |
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Symbols | Description | Min | Max | Unit | Input Supply Voltage | V |
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T_STG | Storage Temperature | -55 | 150 | °C |
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anchor | Table_TS_ROC |
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title | Recommended operating conditions. |
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Parameter | Min | Max | Units | Reference Document | Vin | 5 | 5 | V | See Xilinx ???? datasheet. | Reference Document |
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T_OPT | -40 | +85 | °C |
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Physical Dimensions
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title | Physical Dimension |
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Currently Offered Variants
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anchor | Table_RH_HRH |
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title | Hardware Revision History |
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Date | Revision | Changes | Documentation Link |
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2019-07-19 | REV0101 | Initial Release | REV01 |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
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anchor | Figure_RV_HRN |
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title | Board hardware revision number. |
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Document Change History
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title | Document change history. |
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Date | Revision | Contributor | Description| |
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type | Flat |
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