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anchor	Table_SIP_Ultra96
title	Ultra96 LS Expansion information

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Schematic	Connected to	Notes
HD_GPIO0...7	Level Translator HP_GPIO[0...7], U1	GPIO
HD_GPIO8...15	Level Translator HP_GPIO[8...15], U3	GPIO
MIO36-37	Level Translator PMOD(SPI)	GPIO0-GPIO1
MIO38, MIO41...43	Level Translator PMOD(SPI)	SPI
VCC_PSAUX	Level Translator, U1-U3-U5-U6 Voltage Regulator, U2	1.8 V
5V	Voltage Regulator, U2 Jumper, J10

Pmod Connectors

The TEP0006 is equipped with three Pmod connectors.

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anchor	Table_SIP_Pmod
title	Pmod Connectors information

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Schematic

Connected to

Notes

HD_GPIO0...7

Level Translator HP_GPIO[0...7], U1

GPIO

HD_GPIO8...15

Level Translator HP_GPIO[8...15], U3

GPIO

MIO36-37

Level Translator PMOD(SPI)

GPIO0-GPIO1

MIO38, MIO41...43

Level Translator PMOD(SPI)

SPI

VCC_PSAUX

Level Translator, U1-U3-U5-U6

Voltage Regulator, U2

1.8 V

5V

Voltage Regulator, U2

Jumper, J10

MIO Pins

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hidden	true
id	Comments

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

Pin	Pmod 1, J1	Pmod 2, J2	Pmod SPI, J4
1	PMOD_HD-GPIO0	PMOD_HD-GPIO8	SS
2	PMOD_HD-GPIO1	PMOD_HD-GPIO9	MOSI
3	PMOD_HD-GPIO2	PMOD_HD-GPIO10	MISO
4	PMOD_HD-GPIO3	PMOD_HD-GPIO11	SCK
5	GND	GND	GND
6	3.3 V	3.3 V	3.3 V
7	PMOD_HD-GPIO4	PMOD_HD-GPIO12	INIT
8	PMOD_HD-GPIO5	PMOD_HD-GPIO13	RESET
9	PMOD_HD-GPIO6	PMOD_HD-GPIO14	Not Connected
10	PMOD_HD-GPIO7	PMOD_HD-GPIO15	Not Connected
11	GND	GND	GND
12	3.3 V	3.3 V	3.3 V

Jumpers

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SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

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anchor	Table_OBP_MIOs
title	MIOs pins

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hidden	true
id	Comments

Notes :

add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs

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hidden	true
id	Comments

Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

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anchor	Table_OBP
title	On board peripherals

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Quad SPI Flash Memory

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id	Comments

Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

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anchor	Table_OBP_SPI
title	Quad SPI interface MIOs and pins

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anchor	Table_OBP_RTC
title	I2C interface MIOs and pins

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anchor	Table_OBP_I2C_RTC
title	I2C Address for RTC

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anchor	Table_OBP_EEP
title	I2C EEPROM interface MIOs and pins

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anchor	Table_OBP_I2C_EEPROM
title	I2C address for EEPROM

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LEDs

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anchor	Table_OBP_LED
title	On-board LEDs

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DDR3 SDRAM

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hidden	true
id	Comments

Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

Part number:
Supply voltage:
Speed:
NOR Flash
Temperature:

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Scroll Title
anchor Table_OBPSIP_ETHPmod
title Ethernet PHY to Zynq SoC connectionsPmod Connectors information
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Bank
Designator
Signal Name
Functionality
ETH1
Connection Between
ETH2
Notes
Signal Description

Clock Sources

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anchor	Table_OBP_CLK
title	Osillators

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Power and Power-On Sequence

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hidden	true
id	Comments

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

Power on-sequence
Power distribution
Voltage monitoring circuit

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

J6

HD_GPIO_15

VCC_PSAUX

J7

HD_GPIO_15

VCC_PSAUX

J10

Voltage select

SDA

5 V, 3.3 V

SDA can be either 5 V or 3.3 V

On-board Peripherals

Page properties

hidden	true
id	Comments

Notes :

add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs

Page properties

hidden	true
id	Comments

Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

Power Supply

Power supply with minimum current capability of xx A for system startup is recommended.

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Scroll Title

anchor	Table_PWR_PCOBP
title	Power ConsumptionOn board peripherals

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Power Input Pin

Typical Current

VIN

TBD*

* TBD - To Be Determined

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Chip/Interface	Designator	Notes
--	--	--

Power and Power-On Sequence

Page properties

hidden	true
id	Comments

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

Power on-sequence
Power distribution
Voltage monitoring circuit

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Power Supply

Power supply with minimum current capability of 1 A for system startup is recommended.

Power Consumption

Scroll Title

anchor	FigureTable_PWR_PDPC
title	Power DistributionConsumption

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Power Input Pin	Typical Current
VIN	TBD*

* TBD - To Be Determined

Power Distribution Dependencies

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anchor	Figure_PWR_PSPD
title	Power SequencyDistribution

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Power Rails

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anchor	Table_PWR_PR
title	Module power rails.

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B2B Connector

JM1 Pin

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B2B Connector

JM2 Pin

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B2B Connector

JM3 Pin

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draw.io Diagram

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Power-On Sequence

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anchor	Figure_PWR_PS
title	Power Sequency

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Power Rails

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Voltage
Scroll Title
anchor Table_PWR_BVPR
title Zynq SoC bank voltagesModule power rails.
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Power Rail Name
B2B Connector
JM1 Pin
B2B Connector
JM2 Pin
B2B Connector
JM3 Pin
Direction
Bank
Schematic Name
Notes

Trenz Electronic Documentation

Versions Compared

Old Version 9

New Version 10

Key

Pmod Connectors

MIO Pins

Jumpers

Quad SPI Flash Memory

LEDs

DDR3 SDRAM

Clock Sources

Power and Power-On Sequence

On-board Peripherals

Power Supply

Power and Power-On Sequence

Power Supply

Power Consumption

Power Distribution Dependencies

Power Rails

Power-On Sequence

Power Rails

Technical Specifications

Absolute Maximum Ratings