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The Trenz Electronic TEP0006 is a Pmod Ultra96 LS Low Speed Expansion adapter.
Refer to http://trenz.org/tep0006-info for the current online version of this manual and other available documentation.
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Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options Key Features' must be split into 6 main groups: - FPGA/Module
- Package:
- Speed:
- Temperature:
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
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- On Board:
- 4x Voltage Level Translators
- 2x Voltag Regulators
- Interface:
- 1x Ultra96 LS Expansion ConnectorHeader (40 Pins)
- 3x Pmod HeaderConnectors
- 3x Jumpers
- Power:
- Dimension: 85 mm x 17 mm
Block Diagram
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| Scroll Title |
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| anchor | Figure_OV_BD |
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| title | TEP0006 block diagram |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 45 |
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| diagramName | TEP0006_OV_BD |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 641 |
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| Scroll Only |
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- PMod 2x6 Host Socke (PMOD 2) ,J2
- PMod 2x6 Host Socke (PMOD 2) ,J1
- Level Translator (HP_GPIO[0..7]) ,U1
- Level Translator (HP_GPIO[8..15]),U3
- Level Translator PMOD(SPI),U6
- Linear Voltage Regulator,U2
- Jumper,J6-J7
- PMod 2x6 Host Socke (SPI),J4
- GROVE,J5
- Level Translator (GROVE) ,U5
- Jumper (Voltage select ),J10
- SMD Header 40 Pos. (Ultra96 LS Expansion ),J3
Initial Delivery State
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Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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Low Speed Expansion Connector
General information about GPIO connection to the Ultra96 LS Expansion connector:
| Scroll Title |
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| anchor | Table_SIP_Ultra96 |
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| title | Ultra96 LS Expansion information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic | Connected to | Notes |
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| HD_GPIO0...7 | Level Translator HP_GPIO[0...7], U1 | GPIO | HD_GPIO8...15 | Level Translator HP_GPIO[8...15], U3 | GPIO | | MIO36-37 | Level Translator PMOD(SPI) | GPIO0-GPIO1 | | MIO38, MIO41...43 | Level Translator PMOD(SPI) | SPI | | VCC_PSAUX | Level Translator, U1-U3-U5-U6 Voltage Regulator, U2 | 1.8 V | | 5V | Voltage Regulator, U2 Jumper, J10 |
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| Scroll Title |
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| anchor | Table_PWR_PR |
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| title | Module power rails. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Power Rail Name | Ultra96 LS Expansion Connector Pin | Direction | Notes |
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| +5V | 37 | Input | Directly to module |
| | VCC_PSAUX35VCC_PSAUX | 35 | Output |
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Technical Specifications
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