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anchor Table_OV_RST title Reset process.
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Reset Button Note HPS cold reset S1 HPS warm reset S3 FPGA reset S4

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anchor Table_SIP_FMC title FMC connectors information
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true FMC Signal Intel Cyclone V Direction I/O Signal Count (Single Ended/Differential) Voltage Level Notes LA0...1 RX 4 / 2 FMC_VADJ Voltage level as visible in table Intel Cyclone V SoC bank voltages. LA3, LA5, LA7, ..., LA33 RX 32 / 16 FMC_VADJ Voltage level as visible in table Intel Cyclone V SoC bank voltages. LA2, LA4, LA6, ..., LA32 TX 32 / 16 FMC_VADJ Voltage level as visible in table Intel Cyclone V SoC bank voltages. CLK0...1 RX 4 / 2 FMC_VADJ Voltage level as visible in table Intel Cyclone V SoC bank voltages.

The FMC connector provides further interfaces like JTAG and I²C:

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According to the JTAGEN and JTAGSEL[1..0] pins the management controller Intel MAX10 (U41), the Intel Cyclone V HPS (U10), the Intel Cyclone V FPGA (U10) or the FMC (J4) can be accessed via the micro USB B connector J13.

JTAG access is controlled by the DIP switches S7 and S8 on the module TEI0022. Please note that the DIP Switches are active low.

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anchor Table_SIP_JTG title JTAG pins connection
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true JTAG selection JTAG Signal State Note S7-3 (JTAGSEL0) S7-4 (JTAGSEL1) S8-4 (JTAGEN) JTAGSEL1 JTAGSEL0 JTAGSEL1 JTAGSEL0 Note X X ON Intel MAX10 ON ON OFF Intel Cyclone V HPS ON OFF OFF Intel Cyclone V FPGA OFF ON OFF FMC

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anchor Table_OBP title On board peripherals
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Chip/Interface Designator Notes 87690680System Controller Intel MAX10 U4187690680 Intel Cyclone V U1087690680 DDR3 SDRAM U26...29 87690680Gigabit Ethernet PHY U187690680 High-Speed USB ULPI PHY U887690680 4-Port USB 2.0 Hub U3387690680 HDMI Transmitter U2387690680 FTDI (JTAG) U2187690680 FTDI (UART) U3087690680 DIP-Switches S2, S7...8 87690680Buttons S1, S3...5 87690680On-Board LEDs D1...15, D17...23, D25 87690680Temperature Sensor U16 QSPI U6, U15 87690680EEPROM U31, U38 87690680Oscillator U32, U34, U48 87690680Programmable Clock Generator U387690680 Power Monitoring U54

System Controller Intel MAX 10

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Please refer to the section "Micro USB Connector (JTAG)".

FTDI (UART)

Please refer to the section "Micro USB Connector (UART)".

DIP-Switches

There are three 4-bit DIP-switches present on the TEI0022 board to configure options and set parameters. The following section describes the functionalities of the particular switches.

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The following figures delivers the power-on sequence information. The figure Power Sequency shows the connections between the power devices and its management. The figure Suggested Power Sequency shows the recommended firmware power-on sequence. For more information about firmware depended power-on sequencing see TEI0022 Intel MAX 10 → Power mangement.

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The voltages +3.3V, +5.0V, and VCC are monitored by the voltage monitor circuit LTC2911 (U54), which generates a reset signal at power-on. A manual reset is also possible as described in the reset table.

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anchor Figure_PWR_VMC title Voltage Monitor Circuit
Scroll Ignore draw.io Diagram border true viewerToolbar true fitWindow false diagramDisplayName lbox true revision 2 diagramName Figure_PWR_VMC simpleViewer true width links auto tbstyle top diagramWidth 661 Scroll Only

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