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Overview

The Trenz Electronic TE0821 is a powerful 4 x 5 cm MPSoC module integrated with a Xilinx Zynq UltraScale+ MPSoC. In addition, the module is equipped with 2x 1 GB DDR4 SDRAM chip, 4Gb up to 128 Gb eMMC chip,  2x 64 MB flash memory for configuration and data storage, as well as powerful switching power supplies for all required voltages. The module is equipped with a Lattice Mach XO2 CPLD for system controlling. 3x Robust high-speed connectors provide a large number of inputs and outputs.

The highly integrated modules are smaller than a credit card and are offered in several variants at an affordable price-performance ratio. Modules with a 4 x 5 cm form factor are completely mechanically and largely electrically compatible with each other.

All components cover at least the industrial temperature range. The temperature range in which the module can be used depends on the customer design and the selected cooling. Please contact us for special solutions.

Refer to http://trenz.org/te0821-info for the current online version of this manual and other available documentation.

Key Features

• SoC/FPGA
  
  • Package: SFVC784
  • Device: ZU2 ...ZU5, *
  • Engine:  EG, CG, EV, *
  • Speed: -1, -1L, -2, -2L, 3, *, **
  • Temperature: I, E, *, **
• RAM/Storage
  • 2x  DDR4 SDRAM,
    • Data Width: 16 Bit
    • Size: 8 Gb, *
    • Speed: 2400 Mbps, ***
  • 2x QSPI boot Flash in dual parallel mode
    • Data Width: 8 Bit
    • Size: 512 Mb Gb, *
  • 1x e.MMC Memory
    • Data Width: 16 Bit
    • Size: 8 Gb, *
  • MAC address serial EEPROM
• On Board
  
  • Lattice MachXO2 CPLD
  • Programmable Clock Generator
  • Hi-speed USB2 ULPI Transceiver
  • 4x LEDS
• Interface
  • 1 Gbps RGMII Ethernet interface
  • Hi-speed USB2 ULPI transceiver with full OTG support
  • Graphic Processor Mali-400 MP2, *
  • 156 x High Performance (HP) und 96 x High Density PL I/Os
  • 4 x serial PS GTR transceivers
    • PCI Express interface
    • SATA 3.1 interface

    • DisplayPort interface with video resolution up to 4k x 2k

    • 2x USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
• Power
  • All power regulators on board
• Dimension
  • 40 x 50 mm
• Note
  • * depends on assembly version
  • ** also non low power assembly options possible
  • *** depends on used U+ Zynq and DDR4 combination
  • Rugged for shock and high vibration

Block Diagram

Main Components

1. Xilinx ZYNQ UltraScale+ MPSoC, U1
2. Red LED (ERR_OUT), D3
3. Green LED (ERR_STATUS), D4
4. Red LED (DONE), D1
5. 10/100/1000 Mbps Energy Efficient Ethernet Transceiver, U8
6. 8Gb DDR4, U2-U3
7. 512 Mbit QSPI flash memory, U7-U17
8. Green User LED, D2
9. B2B connector Samtec Razor Beam, JM1
10. Programmable clock generator, U10
11. USB2.0 Transceiver,  U18
12. B2B connector Samtec Razor Beam, JM3
13. B2B connector Samtec Razor Beam, JM2
14. 8 GByte eMMC memory, U6
15. Lattice Semiconductor MachXO2 System Controller CPLD, U21

Additional assembly options are available for cost or performance optimization upon request.

Initial Delivery State

Configuration Signals

Two different firmware versions are available, one with the QSPI boot option and other with the SD Card boot option.

Please refer to the TE0821 CPLD.

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

For detailed information about the pin-out, please refer to the Pin-out table.

JTAG Interface

JTAG access to the Xilinx Zynq UltraScale+ is applicable by using Lattice MachXO CPLD  through B2B connector JM2.

MGT Lanes

There are 4x MGT Lanes connected to FPGA Bank 505-GTR. The Xilinx Zynq UltraScale+ device used on the TE0821 module has 4 GTR transceivers. All 4 are wired directly to B2B connector JM3. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, FPGA bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

Gigabit Ethernet

On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 chip. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 25MHz oscillator (U11), the 125MHz output clock is left unconnected.

System Controller CPLD

Special purpose pins are connected to System Controller CPLD and have following default configuration:

Please check the entire information at TE0821 CPLD.

USB Interface

USB PHY is provided by Microchip USB3320. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V. Reference clock input for the USB PHY is supplied by the on-board 52.00 MHz oscillator (U14). 

I2C Interface

On-board I²C devices are connected to MIO38 (SCL) and MIO39 (SDA) which are configured as I²C0 by default. Addresses for on-board I²C slave devices are listed in the table below:

MIO Pins

Test Points

On-board Peripherals

Quad SPI Flash Memory

The TE0821 is equipped with dual Flash Memory, U7, U17.  Two quad SPI compatible serial bus flash MT25QU512ABB8E12-0SIT memory chips are provided for FPGA configuration file storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.

EEPROM

There is a 2Kb EEPROM provided on the module TE0821.

LEDs

DDR4 SDRAM

The TE0821 SoM has dual 8 Gb volatile DDR4 SDRAM IC for storing user application code and data.

• Part number: K4A8G165WB-BIRC
• Supply voltage: 1.2V
• Speed: 2400 Mbps
• Temperature: -40 ~ 95 °C

System Controller CPLD

The System Controller CPLD (U21) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.

See also TE0821 System Controller CPLD page. 

GigaBit Ethernet

On-board Gigabit Ethernet PHY (U8) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the ZynqMP Ethernet3 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.00 MHz oscillator (U11).

USB2.0 Transceiver

Hi-speed USB ULPI PHY (U18) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO52..63, bank 502. The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.00 MHz oscillator (U14).

eMMC Flash Memory

eMMC Flash memory device(U6) is connected to the ZynqMP PS MIO bank 500 pins MIO13..MIO23. eMMC chips IS21ES08G-JCLI (FLASH - NAND Speicher-IC (64 Gb x 1) MMC ) is used.

Clock Sources

Programmable Clock Generator

There is a Silicon Labs I²C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I²C bus address 0x70 or 0x71. Default address is 0x70, IN4/I2C_LSB pin must be set to high for address 0x71.

A 25.00 MHz oscillator is connected to the pin IN3 and is used to generate the output clocks. The oscillator has its output enable pin permanently connected to 1.8V power rail, thus making output frequency available as soon as 1.8V is present. Three of the Si5338 clock outputs are connected to the FPGA. One is connected to a logic bank and the other two are connected to the GTR banks.

Once running, the frequency and other parameters can be changed by programming the device using the I²C bus connected between the FPGA (master) and clock generator (slave). For this, proper I²C bus logic has to be implemented in FPGA.

Power and Power-On Sequence

Power Supply

Power supply with minimum current capability of 3 A for system startup is recommended.

Power Consumption

* TBD - To Be Determined

Power Distribution Dependencies

Power-On Sequence

Power Rails

Bank Voltages

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 40 mm × 50 mm.  Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: 8 mm.

PCB thickness: 1.74 mm.

Currently Offered Variants 

Revision History

Hardware Revision History

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

Disclaimer

it's nearly like TE0820 → main different HD Banks to B2B instead of HP.

Some sources are available: TE0821 Resources