Page History
...
- Xilinx Kintex UltraScale FPGA (XCKU035 or XCKU040)
- 2 banks of 1024 MByte DDR4 SDRAM, 32bit wide memory interface(each DDR 16bit separate)
- 512 Mbit (64 MByte) QSPI Flash
- 3 x Samtec Razor Beam LSHM B2B, 260 terminals total
- 60 x HR I/Os
- 84 x HP I/Os
- 8 x GTH transceiver lanes (TX/RX)
- 2 x MGT external clock inputs - Clocking
- Si5338 - 4 output PLLs, GT and PL clocks
- 200 MHz LVDS oscillator - All power supplies on-board, single power source operation
- Evenly spread supply pins for optimized signal integrity
- Size: 40 x 50 mm
- 3 mm mounting holes for skyline heat spreader
- Rugged for industrial applications
...
Date | Revision | Contributors | Description | ||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
|
|
| ||||||||||||||||||||||||||
2018-08-07 | v.69 | Ali Naseri |
| ||||||||||||||||||||||||||
2018-07-13 | v.68 | Ali Naseri |
| ||||||||||||||||||||||||||
2018-07-10 | v.58 | John Hartfiel |
| ||||||||||||||||||||||||||
2018-03-13 | v.57 | Jan Kumann, Ali Naseri |
| ||||||||||||||||||||||||||
-- | all |
|
|
Table 18: Document change history
...
Overview
Content Tools