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Scroll Title
anchorTable_DIP_2
titleDIP Switches S5 (CPLD Firmware depended)

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Overview 5DefaultDescription
S5-1ON
  • ON(1), ON(2) - Default, boot from SD/microSD or SPI Flash if no SD is detected
  • OFF(1), ON(2) - Boot from eMMC
  • ON(1), OFF(2) - Boot mode  PJTAG0
  • OFF(1), OFF(2) - Boot mode main  JTAG
S5-2ON
S5-3OFFUser Input to SoC over RGPIO interface
S5-4OFFVADJ OFF(1.8V2V), ON(1.2V8V)



Scroll Title
anchorTable_BUT_1
titleButtons (CPLD Firmware depended)

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Overview 1;3DefaultDescription
S1High

Negative Reset Button, alternative Enclosure over J10-7/J10-5

  • Press appr. 1sec for PS Soft Reset (PS_SRST_B)*
  • Press appr 3 sec for PS POR Reset
S2High

Negative Power Button, alternative Enclosure over J10-6/J10-8

  • Press appr. 1sec for power on/off
  • Press appr 3 sec force power of  without power down sequencing

*Note: PS_SRST_B igrnores mode pins and do not reset all registers, see UG1085 table 38-1

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