Page History

Template Revision 2.

Important General Note:

• If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

• Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

  • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

    • Figure template:

      Scroll Title
      anchor Figure_anchorname title Text
      Scroll Ignore Create DrawIO object here: Attention if you copy from other page, objects are only linked. Scroll Only image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

      
      

    • Table template:

      • Layout macro can be use for landscape of large tables

    • 
      

      Scroll Title
      anchor Table_tablename title Text
      Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Example Comment 1 2

      
      

  • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

    • <type>_<main section>_<name>

      • type: Figure, Table
      • main section:
        
        • "OV" for Overview
        • "SIP" for Signal Interfaces and Pins,
        • "OBP" for On board Peripherals,
        • "PWR" for Power and Power-On Sequence,
        • "B2B" for Board to Board Connector,
        • "TS" for Technical Specification
        • "VCP" for Variants Currently in Production
        •  "RH" for Revision History
      • name: custom, some fix names, see below
    • Fix names:
      

      • "Figure_OV_BD" for Block Diagram

      • "Figure_OV_MC" for Main Components

      • "Table_OV_IDS" for Initial Delivery State

      • "Table_PWR_PC" for Power Consumption

      • "Figure_PWR_PD" for Power Distribution
      • "Figure_PWR_PS" for Power Sequence
      • "Figure_PWR_PM" for Power Monitoring
      • "Table_PWR_PR" for Power Rails
      • "Table_PWR_BV" for Bank Voltages

      • "Table_TS_AMR" for Absolute_Maximum_Ratings

      • "Table_TS_ROC" for Recommended_Operating_Conditions

      • "Figure_TS_PD" for Physical_Dimensions
      • "Table_VCP_SO" for TE_Shop_Overview

      • "Table_RH_HRH" for Hardware_Revision_History

      • "Figure_RH_HRN" for Hardware_Revision_Number
      • "Table_RH_DCH" for Document_Change_History
  • Use Anchor in the document: add link macro and add "#<anchorname>
  • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>

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Note for Download Link of the Scroll ignore macro:

• Link to the base folder of the module (remove de/ or en/ from the URL):
  Example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5_Carriers/TE0728/

Download PDF version of this document.

Notes :

• short description of the PCB

• Short Link of the wiki resources reference:

  • Use short link the Wiki Resource page, for example: http://trenz.org/te0728-info

  • List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features'  must be split into 6 main groups for modules and mainboards:

• SoC/FPGA
  
  • Package: SFVC784
  • Device: ZU2...ZU5*
  • Engine: CG, EG, EV*
  • Speed: -1LI, -2LE,*, **
  • Temperature: I, E,*, **
• RAM/Storage
  • Low Power DDR4 on PS
    • Data width: 32bit
    • Size: def. 2GB*
    • Speed:***
  • eMMC
    • Data width: 8Bit
    • size: def. 8GB *
  • QSPI boot Flash in dual parallel mode (size depends on assembly version)
    • Data width: 8bit
    • size: def. 128MB *
  • HyperRAM/Flash (optional, default not assembled)
    • size:*
  • MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
• On Board
  
  • Lattice LCMXO2
  • PLL SI5338
  • Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
  • Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
• Interface
  • 132 x HP PL I/Os (3 banks)
  • ETH
  • USB
  • 4 GTR (for USB3, Sata, PCIe, DP)
  • MIO for UART
  • MIO for SD
  • MIO for PJTAG
  • JTAG
  • Ctrl
• Power
  
  • 3.3V-5V Main Input
  • 3.3V Controller Input
  • Variable Bank IO Power Input
• Dimension
  • 4 cm x 5 cm
• Notes
  • * depends on assembly version
  • ** also non low power assembly options possible
  • *** depends on used U+ Zynq and DDR4 combination

Key Features'  must be split into 6 main groups for carrier:

• Modules
  
  • TE0808, TE807, TE0803,...
• RAM/Storage
  • E.g. SDRAM, SPI
• On Board
  
  • E.g. CPLD, PLL
• Interface
  • E.g. ETH, USB, B2B, Display port
• Power
  • E.g. Input supply voltage
• Dimension

add drawIO object here.

Notes :

• Picture of the PCB (top and bottom side) with labels of important components
• Add List below

Notes :

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

• Overview of Boot Mode, Reset, Enables.