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Template Revision 2.6 7 - on construction

Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"

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Notes :

  • Add basic key futures, which can be tested with the design


Excerpt
  • Vitis/Vivado 20182019.32
  • TEBF0808
  • Linux
  • USB
  • ETH
  • MAC from EEPROM
  • PCIe
  • SATA
  • SD
  • I2C
  • RGPIO
  • DP
  • user LED access
  • Modified FSBL for Si5338 programming
  • Special FSBL for QSPI Programming

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titleDesign Revision History

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DateVivadoProject BuiltAuthorsDescription
2020-01-272019.2TE0807-StarterKit_noprebuilt-vivado_2019.2-build_4_20200127075822.zip
TE0807-StarterKit-vivado_2019.2-build_4_20200127075809.zip
John Hartfiel
  • 2019.2 update
  • Vitis support
  • FSBL SI programming procedure update 
  • petalinux device tree and u-boot update
2019-05-222018.3TE0807-StarterKit-vivado_2018.3-build_06_20190522132448.zip
TE0807-StarterKit_noprebuilt-vivado_2018.3-build_06_20190522132504.zip
John Hartfiel
  • TE Script update
  • rework of the FSBLs
  • some additional Linux features
  • MAC from EEPROM
  • new assembly variants
  • remove special compiler flags, which was needed in 2018.2
  • ES2 prebuilt files are not included
2019-02-072018.2TE0807-StarterKit_noprebuilt-vivado_2018.2-build_04_20190207111631.zip
TE0807-StarterKit-vivado_2018.2-build_04_20190207111616.zip
John Hartfiel
  • new assembly variant
2018-09-042018.2TE0807-StarterKit_noprebuilt-vivado_2018.2-build_03_20180904122245.zip
TE0807-StarterKit-vivado_2018.2-build_03_20180904121600.zip
John Hartfiel
  • small petalinux changes
  • IO renaming
  • PL Design changes
  • additional notes for FSBL generated with Win SDK
  • changed *.bif
2018-05-242017.4TE0807-StarterKit_noprebuilt-vivado_2017.4-build_10_20180524150124.zip
TE0807-StarterKit-vivado_2017.4-build_10_20180524150106.zip
John Hartfiel
  • solved Linux Flash issue
2018-02-062017.4TE0807-StarterKit_noprebuilt-vivado_2017.4-build_05_20180206082637.zip
TE0807-StarterKit-vivado_2017.4-build_05_20180206082621.zip
John Hartfiel
  • same CLK for VIO
2018-02-052017.4TE0807-StarterKit-vivado_2017.4-build_05_20180205101252.zip
TE0807-StarterKit_noprebuilt-vivado_2017.4-build_05_20180205101306.zip
John Hartfiel
  • solved JTAG/Linux issue
2018-01-182017.4TE0807-StarterKit_noprebuilt-vivado_2017.4-build_05_20180118152938.zip
TE0807-StarterKit-vivado_2017.4-build_05_20180118152922.zip
John Hartfiel
  • initial release


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titleSoftware

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SoftwareVersionNote
VivadoVitis20182019.32needed
SDK2018.3needed
PetaLinux2018.3needed
, Vivado is included into Vitis installation
PetaLinux2019.2needed
SI ClockBuilder Pro---optional


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titleHardware Modules

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Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0807-01-07EV-ES   ES   es2_2gb      REV01    2GB      64GB       NA         NA     Slower DDR Speed Not longer supported by vivado
TE0807-02-07EV-1E   7ev_1e_4gb   REV02    4GB      64GB       NA         NA     NA           NA                               
TE0807-02-07EV-1EK  7ev_1e_4gb   REV02    4GB      64GB       NA         NA     with heat sink   

Note: Design contains also Board Part Files for TE0807 only configuration, this boart part files are not used for this reference design.

Design supports following carriers:

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anchorTable_HWC
titleHardware Carrier

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Additional HW Requirements:

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titleAdditional Hardware

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Content

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Notes :

  • content of the zip file

For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

Design sources
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sink                 
TE0807-02-4BE21-A   4eg_1e_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-7DE21-A   7ev_1e_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-7DI21-C   7ev_1i_4gb   REV02    4GB      128MB      NA         NA     without encryption             
TE0807-02-7DI21-A   7ev_1i_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-4AI21-A   4cg_1i_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-5AI21-A   5cg_1i_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-7AI21-A   7cg_1i_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-7DI24-A   7ev_1i_4gb   REV02    4GB      512MB      NA         NA     NA                               
TE0807-02-7DE21-AK  7ev_1e_4gb   REV02    4GB      128MB      NA         NA     with heat sink             


Note: Design contains also Board Part Files for TE0807 only configuration, this boart part files are not used for this reference design.

Design supports following carriers:

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titleHardware Carrier

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TypeCarrier ModelLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration

Additional Sources

TEBF0808Used as reference carrier. Important: CPLD Firmware REV07 or newer is recommended


Additional HW Requirements:

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titleAdditional design sourcesHardware

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TypeAdditional HardwareLocationNotes
SI5345<design name>/misc/Si5345SI5345 Project with current PLL Configuration
init.sh<design name>/sd/Additional Initialization Script for Linux

Prebuilt

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Notes :

  • prebuilt files
  • Template Table:content of the zip file

For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

PFPrebuilt filesPrebuilt files (only on ZIP with prebult content)
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Design sources
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title

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File
Type
File-Extension
Location
Description
Notes
BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

Debian SD-Image

*.img

Debian Image for SD-Card

Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File

MCS-File

*.mcs

Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

MMI-File

*.mmi

File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

SREC-File

*.srec

Converted Software Application for MicroBlaze Processor Systems

Scroll Title
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
Vitis<design name>/sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration


Additional Sources

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TypeLocationNotes
SI5345<design name>/misc/Si5345SI5345 Project with current PLL Configuration
init.sh<design name>/sd/Additional Initialization Script for Linux


Prebuilt

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  • prebuilt files
  • Template Table:

    • Scroll Title
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      titlePrebuilt files

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      File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Hardware-Platform-Specification-Files*.
hdf
    • xsaExported Vivado Hardware Specification for
SDK/HSI
    • Vitis and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

Design Flow

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Notes :
  • Basic Design Steps

  • Add/ Remove project specific description

Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
    Image Removed
  2. Press 0 and enter to start "Module Selection Guide"
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
  5. Create Project
    1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
                Important: Use Board Part Files, which ends with *_tebf0808
  6. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  7. Create Linux (bl31.elf, uboot.elf and image.ub) with exported HDF
    1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
        Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
  8. Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder
    1. prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
  9. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

Launch

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Note:

  • Programming and Startup procedure
    • SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems




Scroll Title
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titlePrebuilt files (only on ZIP with prebult content)

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File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems


Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

Design Flow

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Notes :
  • Basic Design Steps

  • Add/ Remove project specific description


Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.


Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality


  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
    Image Added
  2. Press 0 and enter to start "Module Selection Guide"
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
    1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
                Important: Use Board Part Files, which ends with *_tebf0808
  5. Create XSA and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (bl31.elf, uboot.elf and image.ub) with exported XSA
    1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
  7. Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder
    1. prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
  8. Generate Programming Files with Vitis
    1. Run on Vivado TCL: TE::sw_run_vitis -all
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
      Note:  TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis

Launch

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Note:

  • Programming and Startup procedure

For basic board setup, LEDs... see: TEBF0808 Getting Started

...

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

...

Get prebuilt boot binaries

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select Create and open delivery binary folder
      Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated

QSPI

Optional for Boot.bin on QSPI Flash and image.ub on SD.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
    Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
             optional "TE::pr_program_flash_binfile -swapp hello_te0803" possible
  4. Copy image.ub on SD-Card

      ...

        1. use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
        2. or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
      1. Set Boot Mode to QSPI-Boot and insered SD.
        1. Depends on Carrier, see carrier TRM.
        2. TEBF0808 change automatically the Boot Mode to SD, if SD is insered, optional CPLD Firmware without Boot Mode changing for mircoSD Slot is available on the download area

      SD

      1. Copy image.ub and Boot.bin on SD-Card.
          For correct
        • use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
        • or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
      2. Set Boot Mode to SD-Boot.
        • Depends on Carrier, see carrier TRM.
      3. Insert SD-Card in SD-Slot.

      ...

      Scroll Title
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      titleVivado Hardware Manager



      System Design - Vivado

      <!-- Description of Block Design,
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      Block Design

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      Code Block
      languageruby
      title_i_io.xdc
      #System Controller IP
      
      #J3:31 LED_HD
      set_property PACKAGE_PIN K11 [get_ports BASE_sc0]
      #J3:41
      set_property PACKAGE_PIN E14 [get_ports BASE_sc5]
      #J3:45
      set_property PACKAGE_PIN C12 [get_ports BASE_sc6]
      #J3:47
      set_property PACKAGE_PIN D12 [get_ports BASE_sc7]
      #J3:32
      set_property PACKAGE_PIN J12 [get_ports BASE_sc10_io]
      #J3:34
      set_property PACKAGE_PIN K13 [get_ports BASE_sc11]
      #J3:36
      set_property PACKAGE_PIN A13 [get_ports BASE_sc12]
      #J3:38
      set_property PACKAGE_PIN A14 [get_ports BASE_sc13]
      #J3:40
      set_property PACKAGE_PIN E12 [get_ports BASE_sc14]
      #J3:42
      set_property PACKAGE_PIN F12 [get_ports BASE_sc15]
      #J3:46 CAN S
      set_property PACKAGE_PIN A12 [get_ports BASE_sc16]
      #J3:48 LED_XMOD
      set_property PACKAGE_PIN B12 [get_ports BASE_sc17]
      #J3:50 CAN TX 
      set_property PACKAGE_PIN B14 [get_ports BASE_sc18]
      #J3:52 CAN RX 
      set_property PACKAGE_PIN C14 [get_ports BASE_sc19]
      
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19]
      
      # PLL
      #J4:74
      #set_property PACKAGE_PIN AF15 [get_ports {si570_clk_p[0]}]
      #set_property IOSTANDARD LVDS [get_ports {si570_clk_p[0]}]
      #set_property IOSTANDARD LVDS [get_ports {si570_clk_n[0]}]
      
      
      
      # Audio Codec
      #LRCLK        J3:49 B47_L9_N
      #BCLK        J3:51 B47_L9_P
      #DAC_SDATA    J3:53 B47_L7_N
      #ADC_SDATA    J3:55 B47_L7_P
      set_property PACKAGE_PIN G14 [get_ports LRCLK ]
      set_property PACKAGE_PIN H14 [get_ports BCLK ]
      set_property PACKAGE_PIN C13 [get_ports DAC_SDATA ]
      set_property PACKAGE_PIN D14 [get_ports ADC_SDATA ]
      set_property IOSTANDARD LVCMOS18 [get_ports LRCLK ]
      set_property IOSTANDARD LVCMOS18 [get_ports BCLK ]
      set_property IOSTANDARD LVCMOS18 [get_ports DAC_SDATA ]
      set_property IOSTANDARD LVCMOS18 [get_ports ADC_SDATA ]
      
      

      Software Design -

      ...

      Vitis

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      Note:
      • optional chapter separate

      • sections for different apps

      For SDK project creation, follow instructions from:SDK Projects

      Vitis

      Application

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      ----------------------------------------------------------

      FPGA Example

      scu

      MCS Firmware to configure SI5338 and Reset System.

      srec_spi_bootloader

      TE modified 20182019.3 2 SREC

      Bootloader to load app or second bootloader from flash into DDR

      Descriptions:

      • Modified Files: blconfig.h, bootloader.c
      • Changes:
        • Add some console outputs and changed bootloader read address.
        • Add bugfix for 2018.2 qspi flash

      xilisf_v5_11

      TE modified 20182019.3 2 xilisf_v5_11

      • Changed default Flash type to 5.

      ----------------------------------------------------------

      Zynq Example:

      zynq_fsbl

      TE modified 20182019.3 2 FSBL

      General:

      • Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
      • Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

      • General Changes: 
        • Display FSBL Banner and Device ID

      Module Specific:

      • Add Files: all TE Files start with te_*
        • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot  platform-top.h)
        • CPLD access
        • Read CPLD Firmware and SoC Type
        • Configure Marvell PHY

      zynq_fsbl_flash

      TE modified 20182019.3 2 FSBL

      General:

      • Modified Files: main.c
      • General Changes:
        •  Display FSBL Banner
        • Set FSBL Boot Mode to JTAG
        • Disable Memory initialisation

      ZynqMP Example:

      ----------------------------------------------------------

      zynqmp_fsbl

      TE modified 20182019.3 2 FSBL

      General:

      • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
      • Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
      • General Changes: 
        • Display FSBL Banner and Device Name

      Module Specific:

      • Add Files: all TE Files start with te_*
        • Si5338 Configuration
        • ETH+OTG Reset over MIO

      zynqmp_fsbl_flash

      TE modified 20182019.3 2 FSBL

      General:

      • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
      • General Changes:
        •  Display FSBL Banner
        • Set FSBL Boot Mode to JTAG
        • Disable Memory initialisation


      zynqmp_pmufw

      Xilinx default PMU firmware.

      ----------------------------------------------------------

      General Example:

      hello_te0820

      Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

      u-boot

      U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

      SDK template in ./sw_lib/sw_apps/ available.

      zynqmp_fsbl

      TE modified 20182019.3 2 FSBL

      General:

      • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
      • Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
      • General Changes: 
        • Display FSBL Banner and Device Name

      ...

      zynqmp_fsbl_flash

      TE modified 20182019.3 2 FSBL

      General:

      • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
      • General Changes:
        •  Display FSBL Banner
        • Set FSBL Boot Mode to JTAG
        • Disable Memory initialisation

      ...

      Start with petalinux-config -c u-boot

      Changes:

      • CONFIG_ENV_IS_NOWHERE=y

      • # CONFIG_ENV_IS_IN_SPI_FLASH is not set

      Change platform-top.h:

      ...

      languagejs

      ...

      • CONFIG_I2C_EEPROM=y

      • CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA

      • CONFIG_SYS_

      ...

      Device Tree

      ...

      languagejs

      ...

      • I2C_EEPROM_ADDR=0x50

      • CONFIG_SYS_I2C_EEPROM_BUS=2

      • CONFIG_SYS_EEPROM_SIZE=256

      • CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0

      • CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0

      • CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1

      • CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0

      Change platform-top.h:

      Code Block
      languagejs

      Device Tree

      Code Block
      languagejs
      /include/ "system-conf.dtsi"
      / {
        chosen {
          xlnx,eeprom = &eeprom;
        };
      };
      
      /* notes:
      serdes: // PHY TYP see: dt-bindings/phy/phy.h
      */
      
      /* default */
      
      /* SD */
      
      &sdhci1 {
      	// disable-wp;
      	no-1-8-v;
      
      };
      
      
      /* USB  */
      
      
      &dwc3_0 {
          status = "okay";
          dr_mode = "host";
          snps,usb3_lpm_capable;
          snps,dis_u3_susphy_quirk;
          snps,dis_u2_susphy_quirk;
          phy-names = "usb2-phy","usb3-phy";
          phys = <&lane1 4 0 2 100000000>;
          maximum-speed = "super-speed";
      };
      
      /* ETH PHY */
      
      &gem3 {
      	phy-handle = <&phy0>;
      	phy0: phy0@1 {
      		device_type = "ethernet-phy";
      		reg = <1>;
      	};
      };
      
      /* QSPI */
      
      &qspi {
          #address-cells = <1>;
          #size-cells = <0>;
          status = "okay";
          flash0: flash@0 {
              compatible = "jedec,spi-nor";
              reg = <0x0>;
              #address-cells = <1>;
       <1>;
              #size-cells = <0><1>;
          status = "okay";
       };
      };
      
      /* I2C */
      
      &i2c0 {
         flash0: flash@0i2cswitch@73 { // u
              compatible = "jedecnxp,spi-norpca9548";
              reg#address-cells = <0x0><1>;
              #address#size-cells = <1><0>;
              #size-cellsreg = <1><0x73>;
             } i2c-mux-idle-disconnect;
      };
      
      /* I2C */
      
      &i2c0 {
              i2cswitch@73i2c@0 { // u
      MCLK TEBF0808     SI5338A, 570FBB000290DG_unassembled
        compatible = "nxp,pca9548";
              #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <0x73><0>;
              i2c-mux-idle-disconnect;
      };
              i2c@2i2c@1 { // PCIeSFP TEBF0808 PCF8574DWR
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <2><1>;
              };
              i2c@3i2c@2 { // i2c SFPPCIe
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <3><2>;
              };
              i2c@4i2c@3 { // i2cSFP1 SFPTEBF0808
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <4><3>;
              };
              i2c@5i2c@4 { // i2cSFP2 EEPROMTEBF0808
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <5><4>;
              };
              i2c@6i2c@5 { // i2cTEBF0808 FMCEEPROM
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <6>;
      
                  si570_2: clock-generator3@5d {
             <5>;
               #clock-cells = <0>;
       eeprom: eeprom@50  {
      	            compatible = "silabsatmel,si57024c08";
      	            reg = <0x50>;
      	   reg      = <0x5d>};
              };
              temperature-stabilityi2c@6 = <50>;
        { // TEBF0808 FMC  
                  factory#address-foutcells = <156250000><1>;
                      clock-frequency#size-cells = <78800000><0>;
                  }reg = <6>;
              };
              i2c@7 { // i2cTEBF0808 USB HUB
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <7>;
              };
          };
          i2cswitch@77 { // u
              compatible = "nxp,pca9548";
              #address-cells = <1>;
              #size-cells = <0>;
              reg = <0x77>;
              i2c-mux-idle-disconnect;
              i2c@0 { // i2cTEBF0808 PMOD P1
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <0>;
              };
              i2c@1 { // i2c Audio Codec
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <1>;
      			/*
                  adau1761: adau1761@38 {
                      compatible = "adi,adau1761";
                      reg = <0x38>;
                  };
      			*/
              };
              i2c@2 { // i2cTEBF0808 FireFlyFirefly A
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <2>;
              };
              i2c@3 { // i2cTEBF0808 FireFlyFirefly B
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <3>;
              };
              i2c@4 { //Module i2c PLLPLL Si5338 or SI5345
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <4>;
              };
              i2c@5 { //TEBF0808 i2c SCCPLD
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <5>;
              };
              i2c@6 { //TEBF0808 Firefly i2cPCF8574DWR
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <6>;
              };
              i2c@7 { // i2cTEBF0808 PMOD P3
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <7>;
              };
          };
      };
      
      
      
      
      

      Kernel

      Start with petalinux-config -c kernel

      ...

      • CONFIG_CPU_IDLE is not set (only needed to fix JTAG Debug issue)

      • CONFIG_CPU_FREQ is not set (only needed to fix JTAG Debug issue)

      • CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set (only needed to fix JTAG Debug issue)CONFIG_EDAC_CORTEX_ARM64=y

      Rootfs

      Start with petalinux-config -c rootfs

      Changes:

      • CONFIG_i2c-tools=y
      • CONFIG_busybox-httpd=y (for web server app)
      • CONFIG_packagegroup-petalinux-utils(util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)

      Applications

      startup

      ...

      See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

      startup

      Script App to load init.sh from SD Card if available.

      webfwu

      Webserver application accemble for Zynq access. Need busybox-httpd

      ...

      Scroll Title
      anchorTable_dch
      titleDocument change history.

      Scroll Table Layout
      orientationportrait
      sortDirectionASC
      repeatTableHeadersdefault
      style
      widths2*,*,3*,4*
      sortByColumn1
      sortEnabledfalse
      cellHighlightingtrue

      DateDocument Revision

      Authors

      Description

      Page info
      modified-date
      modified-date
      dateFormatyyyy-MM-dd

      Page info
      infoTypeCurrent version
      prefixv.
      typeFlat

      Page info
      modified-user
      modified-user

      • new assembly variants
      • Release 2019.2
      29-05-22v.16John Hartfiel
      • Release 2018.3

      2019-09-04

      v.13John Hartfiel
      • Release 2018.2

      2018-07-20

      v.12John Hartfiel
      • Design update

      2018-04-30

      v.10John Hartfiel
      • Update known issues

      2018-02-08

      v.9John Hartfiel
      • Design update
      2018-01-29v.4John Hartfiel
      • Update known issues
      2018-01-18v.3John Hartfiel
      • Release 2017.4

      All

      Page info
      modified-users
      modified-users



      ...