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Template Revision 1.9 - on construction

Design Name always "TE Series Name" + optional CPLD Name + "CPLD"


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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware


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Table of contents

Table of Contents
outlinetrue

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  • JTAG routing
  • Boot Mode settings
  • LEDPower Managment

Firmware Revision and supported PCB Revision

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output Firmware variantoutput PHY_LED1
Name / opt. VHD NameDirectionPinBank PowerDescriptionNote:
PCB REV01 REV02 Connection
C_TCK     in303.3VINJTAG B2B
C_TDI     in323.3VINJTAG B2B
C_TDO     out13.3VINJTAG B2B
C_TMS     in293.3VINJTAG B2BEN1       
PG_FPD      in273.3VINPower Enable from B2B Connector (Positive Enable) / Used only for PGOOD feedbackGOOD from SOC FPD regulators
RESINinoutUser_LEDout43.3VINuser defined or status, see LED description
1.8V input ERR_OUT(PS_ERROR_OUT)Reset control and minitoring
EN_MGToutN.C.53.3VIN/ currently_not_used1.8V  input ERR_STATUS as inputenable GTR Power Domain
JTAGEN    in263.3VINEnable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access)
MODE      in253.3VINBoot Mode for Zynq/ZynqMP Devices (Flash or SD)
MODE0     out121.8VZynqMP Boot Mode Pin 0
MODE1     out131.8VZynqMP Boot Mode Pin 1
MODE2     out141.8VZynqMP Boot Mode Pin 2
MODE3     out161.8VZynqMP Boot Mode Pin  3
NOSEQ     inout233.3VINusage CPLD Variant depends
PGOOD     outinout283.3VINModule Power Good (only Feedback from EN1).(FPD + MGT(if not disabled by user))
PG_MGTPHY_LED1  in171.8VETH PHY LED1 / currently_not_usedPower Good of GTR power domain
TCK     out91.8VJTAG ZynqMP
TDI       out81.8VJTAG ZynqMP
TDO       in101.8VJTAG ZynqMP
TMS       out111.8VJTAG ZynqMP
X0        in20VCCO_65FPGA IO (FPGA Pin H1) / Enable User LED (negative)X0 X1 can be used to disable MGT Power
X1        in21VCCO_65FPGA IO (FPGA Pin J1)/ Connect to User LEDX0 X1 can be used to disable MGT Power

Functional Description

JTAG

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Note

NOSEQ*: Please check the carrier board documentation, before using the SD/QSPI/JTAG  firmware variant on TE0820TE0823. In the most cases special carrier CPLD firmware is needed.

Power

PGOOD is EN1. There is no additional power management controlled by CPLD.

LED

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*It's recommended to forward this signal to a carrier LED if status check is needed.

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is  zero if PG_FPD is low or  if PG_MGT is low (as long as it is enabled by user) otherwise it's high impedance

Appx. A: Change History

For PCB REV01 and REV02 Documentation available on: TE0820-REV01_REV02 CPLD

Revision Changes

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  • PCB REV03 support only

  • X1 is input for USER LED

  • X0 select  X0 or Firmware Blink status to User LE

  • blink modes for QSPI/SD firmware

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  • REV01 to REV02
    • initial release
    • Boot Mode variants
    • X1
    • Remove ERR_STATUS

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

1REV04created-user

DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription


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REV01REV03John Hartfiel
  • Revision 04 finished
  • separate page for PCB REV01 and REV02
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REV04REV03

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