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Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template (note: inner scroll ignore/only only with drawIO object):

        Scroll Title
        anchorFigure_xyz
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)

      • Scroll Title
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        titleText

        Scroll Table Layout
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        ExampleComment
        12



  • ...


Scroll pdf ignore

Table of contents

Table of Contents
outlinetrue

Overview

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Notes :

Refer to http://trenz.org/te0820-info for the current online version of this manual and other available documentation.

Key Features

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Notes :

  • Add basic key futures, which can be tested with the design

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Excerpt
  • Vitis/Vivado 2019.2
  • PetaLinux
  • Linux Debian 9 (Stretch) or Linux Ubuntu 18.04 (Bionic Beaver)
  • HDMI
  • SD
  • ETH (use EEPROM MAC)
  • USB
  • I2C
  • TE0701
  • RTC
  • Modified FSBL for SI5338 programming and DMA (for HDMI)
  • Special FSBL for QSPI programming

Revision History

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Notes :

  • add every update file on the download
  • add design changes on description

...

Scroll Title
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titleDesign Revision History

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DateVivadoProject BuiltAuthorsDescription
2020-03-272019.2

TE0820-HDMI701_noprebuilt-vivado_2019.2-build_8_20200330084946.zip
TE0820-HDMI701-vivado_2019.2-build_8_20200330084931.zip

Mohsen Chamanbaz
  • initial release


Release Notes and Know Issues

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Notes :
  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if  issue fixed

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Scroll Title
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titleKnown Issues

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IssuesDescriptionWorkaroundTo be fixed version
No known issues---------


Requirements

Software

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Notes :

  • list of software which was used to generate the design

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titleSoftware

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SoftwareVersionNote
Vitis2019.2needed, Vivado is included into Vitis installation
PetaLinux2019.2needed

SD Card Formatter


format SD Card

Win32 DiskImager


born generated image on SD


Hardware

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Notes :

  • list of software which was used to generate the design

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Scroll Title
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titleAdditional Hardware

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Additional HardwareNotes
CoolerIt's recommended to use cooler on ZynqMP device
USB CableConnect to USB2 or better USB3 Hub for proper power supply over USB
MonitorDELL Model Number: U2412Mc
Micro USB to USB A AdapterAdapter for USB Hub
USB HUBTo connnect Mouse and Keyboard simultaneously
Keyboardneed for Ubuntu/Debian GUI
Mouseneed for Ubuntu/Debian GUI
HDMI Cable--


Content

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Notes :

  • content of the zip file

For general structure and of the reference design, see see Project Delivery - Xilinx AMD devices

Design Sources

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titleDesign sources

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TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
Vitis<design name>/sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration


Additional Sources

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titleAdditional design sources

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TypeLocationNotes
mkdebian_stretch.sh<design name>/os/petalinuxcreate Debian image
mkubuntu_BionicBeaver.sh<design name>/os/petalinuxcreate Ubuntu image


Prebuilt

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Notes :

  • prebuilt files
  • Template Table:

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      titlePrebuilt files

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      File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Hardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems



...

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titlePrebuilt files (only on ZIP with prebult content)

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File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

Debian SD-Image

*.img

Debian Image for SD-Card

Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems


Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

...

Design Flow

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Notes :
  • Basic Design Steps

  • Add/ Remove project specific description

...

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

...

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
  2. Press 0 and enter to start "Module Selection Guide"
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
    1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see also TE Board Part Files
  5. Create XSA and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (bl31.elf, uboot.elf and image.ub) with exported XSA
    1. XSA is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
    3. Build the Debian image/Ubuntu image file with executing the "mkdebian_stretch.sh"/"mkubuntu_BionicBeaver.sh" file in Linux Terminal
  7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
  8. Generate Programming Files with Vitis
    1. Run on Vivado TCL: TE::sw_run_vitis -all
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
      Note:  TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis

Launch

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Note:

  • Programming and Startup procedure

Programming

Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging  AMD Development Tools#XilinxSoftwareProgrammingandDebugging

Get prebuilt boot binaries

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select Create and open delivery binary folder
      Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated

QSPI

Not used in this Example.

SD

  1. Format the SD Card with SD Card Formatter or other tool
  2. Write the Debian image or Ubuntu image file on SD Card with Win32DiskImager
  3. Copy Petalinux  image.ub and Boot.bin on SD-Card.
    • use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  4. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  5. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section TE0820 HDMI701#Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card as Boot Mode
    Note: On TE0701 Default  Firmware Boot Mode is selected via SD card (insered SD Card for SD Boot Mode)
  4. Connect HDMI to Monitor
  5. Connect USB Adapter with Hub and Mouse+Keyboard
  6. Power On PCB
    Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
  3. You can use Linux shell now.
  4. Debian Desktop
    1. Debian Desktop will be started automatically
    2. Use connected mouse + keyboard for interaction with GUI
    3. Web Browser Dillo open console and type dillo or use browser
    4. open console and start video or audio with "mplayer <video or audio file>"
  5. Ubuntu Desktop
    1. Ubuntu Desktop will be started automatically
    2. Use connected mouse + keyboard for interaction with GUI
    3. Web Browser Mozilla firefox can be used.
    4. Audio or Vider file can also be performed directly in GU

Vivado HW Manager

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Note:

  • Add picture of HW Manager

  • add notes for the signal either groups or topics, for example:

    Control:

    • add controllable IOs with short notes..

    Monitoring:

    • add short notes for signals which will be monitored only
    • SI5338 CLKs:
      • Set radix from VIO signals to unsigned integer. Note: Frequency Counter is inaccurate and displayed unit is Hz
      • expected CLK Frequ:...

...

Scroll Title
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titleVivado Hardware Manager

System Design - Vivado

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Note:

  • Description of Block Design, Constrains... BD Pictures from Export...

Block Design

Scroll Title
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titleBlock Design

PS Interfaces

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Note:

  • optional for Zynq / ZynqMP only

  • add basic PS configuration

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Scroll Title
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titlePS Interfaces

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TypeNote
DDR
QSPIMIO
SD0MIO
SD1MIO
I2C0MIO
I2C1EMIO
UART0MIO
GPIO0MIO
SWDT0..1
TTC0..3
GEM3MIO
USB0MIO


Constrains

Basic module constrains

Code Block
languageruby
title_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

Code Block
languageruby
title_i_hdmi.xdc
 TODO replace loc constrains with correct one for TE0820
#
# TE0701 I2C Bus
#
set_property PACKAGE_PIN P7 [get_ports IIC_1_scl_io]
set_property PACKAGE_PIN P6 [get_ports IIC_1_sda_io]
set_property IOSTANDARD LVCMOS18 [get_ports IIC_1_scl_io]
set_property IOSTANDARD LVCMOS18 [get_ports IIC_1_sda_io]

#
# ADV7511 Interface
#
set_property PACKAGE_PIN L6 [get_ports hdmi_out_clk]
set_property PACKAGE_PIN L7 [get_ports hdmi_out_de]
set_property PACKAGE_PIN K4 [get_ports hdmi_out_hsync]
set_property PACKAGE_PIN K3 [get_ports hdmi_out_vsync]
set_property PACKAGE_PIN T6 [get_ports {hdmi_out_data[0]}]
set_property PACKAGE_PIN R6 [get_ports {hdmi_out_data[1]}]
set_property PACKAGE_PIN V9 [get_ports {hdmi_out_data[2]}]
set_property PACKAGE_PIN U9 [get_ports {hdmi_out_data[3]}]
set_property PACKAGE_PIN T7 [get_ports {hdmi_out_data[4]}]
set_property PACKAGE_PIN N8 [get_ports {hdmi_out_data[5]}]
set_property PACKAGE_PIN R7 [get_ports {hdmi_out_data[6]}]
set_property PACKAGE_PIN N9 [get_ports {hdmi_out_data[7]}]
set_property PACKAGE_PIN Y8 [get_ports {hdmi_out_data[8]}]
set_property PACKAGE_PIN V8 [get_ports {hdmi_out_data[9]}]
set_property PACKAGE_PIN W8 [get_ports {hdmi_out_data[10]}]
set_property PACKAGE_PIN U8 [get_ports {hdmi_out_data[11]}]
set_property IOSTANDARD LVCMOS18 [get_ports hdmi_*]

set_property PACKAGE_PIN H7 [get_ports {cec_clk[0]}]
set_property PACKAGE_PIN M8 [get_ports {ct_hpd[0]}]
set_property PACKAGE_PIN J7 [get_ports {ls_oe[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {cec_clk[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {ct_hpd[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {ls_oe[0]}]

Software Design - Vitis

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Note:
  • optional chapter separate

  • sections for different apps

For SDK project creation, follow instructions from:

Vitis

Application

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----------------------------------------------------------

FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2019.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

  • Modified Files: blconfig.h, bootloader.c
  • Changes:
    • Add some console outputs and changed bootloader read address.
    • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2019.2 xilisf_v5_11

  • Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

zynq_fsbl

TE modified 2019.2 FSBL

General:

  • Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot  platform-top.h)
    • CPLD access
    • Read CPLD Firmware and SoC Type
    • Configure Marvell PHY

zynq_fsbl_flash

TE modified 2019.2 FSBL

General:

  • Modified Files: main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2019.2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
  • Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2019.2 FSBL

General:

  • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation


zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis  is used to generate Boot.bin.

Template location: ./sw_lib/sw_apps/

zynqmp_fsbl

TE modified 2019.2 FSBL

General:

...

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • ETH+OTG Reset over MIO
    • DMA for HDMI

zynqmp_fsbl_flash

TE modified 2019.2 FSBL

General:

  • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

U-Boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design -  PetaLinux

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Note:
  • optional chapter separate

  • sections for linux

  • Add "No changes." or "Activate: and add List"

For PetaLinux installation and  project creation, follow instructions from:

Config

Start with petalinux-config or petalinux-config --get-hw-description

...

  • CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
  • CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC=""
  • # CONFIG_SUBSYSTEM_ROOTFS_INITRAMFS is not set

  • # CONFIG_SUBSYSTEM_ROOTFS_INITRD is not set

  • # CONFIG_SUBSYSTEM_ROOTFS_JFFS2 is not set

  • # CONFIG_SUBSYSTEM_ROOTFS_NFS is not set

  • CONFIG_SUBSYSTEM_ROOTFS_SD=y

  • # CONFIG_SUBSYSTEM_ROOTFS_OTHER is not set

  • # CONFIG_SUBSYSTEM_BOOTARGS_AUTO is not set

  • CONFIG_SUBSYSTEM_USER_CMDLINE="console=ttyPS0,115200 earlycon clk_ignore_unused earlyprintk root=/dev/mmcblk1p2 rootfstype=ext4 rw rootwait cma=256M"

  • CONFIG_SUBSYSTEM_DEVICETREE_FLAGS=""

  • # CONFIG_SUBSYSTEM_DTB_OVERLAY is not set

  • # CONFIG_SUBSYSTEM_REMOVE_PL_DTB is not set

U-Boot

Start with petalinux-config -c u-boot

...

  • CONFIG_ENV_IS_NOWHERE=y

  • # CONFIG_ENV_IS_IN_SPI_FLASH is not set

  • CONFIG_I2C_EEPROM=y

  • CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA

  • CONFIG_SYS_I2C_EEPROM_ADDR=0x50

  • CONFIG_SYS_I2C_EEPROM_BUS=0

  • CONFIG_SYS_EEPROM_SIZE=256

  • CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0

  • CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0

  • CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1

  • CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0


Device Tree

Code Block
languagejs
/include/ "system-conf.dtsi"
/ {
	chosen {
    		xlnx,eeprom = &eeprom;
		    bootargs= "console=ttyPS0,115200 earlycon clk_ignore_unused earlyprintk root=/dev/mmcblk1p2 rootfstype=ext4 rw rootwait cma=256M";

  	};
};


/ {
	#address-cells = <2>;
	#size-cells = <2>;
	memory@0{
	  device-type = "memory";
	  reg = <0x000000000 0x00000000 0x00000000 0x80000000>;
	};	
	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		hdmi_fb_reserved_region: framebuffer@7FC00000 {
		    compatible = "removed-dma-pool";
		    //compatible = "shared-dma-pool";
		    //compatible = "xlnx,reserved-memory";
		    no-map;
		    reg = <0x0 0x7FC00000 0x0 0x400000>;
		};
      	};
 
	hdmi_fb: framebuffer@0x7FC00000 {           // HDMI out
		compatible = "simple-framebuffer";
		reg = <0x0 0x7FC00000 0x0 (1280 * 720 * 4)>;    // 720p
		width = <1280>;                         // 720p
		height = <720>;                         // 720p
		stride = <(1280 * 4)>;                  // 720p
		format = "a8b8g8r8";
		status = "okay";
	};
};

&axi_vdma_0 {
   status = "disabled";
};
  
&v_tc_0 {
    //xilinx-vtc: probe of 43c20000.v_tc failed with error -2
    status = "disabled";
};

/* SDIO */

&sdhci1 {
   status = "okay";
   disable-wp;
   no-1-8-v;
};

/* ETH PHY */
&gem3 {

	status = "okay";
  ethernet_phy0: ethernet-phy@0 {
		compatible = "marvell,88e1510";
		device_type = "ethernet-phy";
    		reg = <1>;
	};
};
/* USB 2.0 */
 
/* USB  */
&dwc3_0 {
    status = "okay";
    dr_mode = "host";
    maximum-speed = "high-speed";
    /delete-property/phy-names;
    /delete-property/phys;
    /delete-property/snps,usb3_lpm_capable;
 	 snps,dis_u2_susphy_quirk;
  	snps,dis_u3_susphy_quirk;
};
   
&usb0 {
    status = "okay";
    /delete-property/ clocks;
    /delete-property/ clock-names;
    clocks = <0x3 0x20>;
    clock-names = "bus_clk";
};




/* QSPI PHY */
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};

&i2c0 {
  eeprom: eeprom@50 { 
     compatible = "atmel,24c08";
     reg = <0x50>;
  };
};



Kernel

Start with petalinux-config -c kernel

...

  • CONFIG_CPU_IDLE is not set (only needed to fix JTAG Debug issue)

  • CONFIG_CPU_FREQ is not set (only needed to fix JTAG Debug issue)

  • CONFIG_EDAC_CORTEX_ARM64=y
  • CONFIG_FB_SIMPLE
  • CONFIG_LOGO
  • CONFIG_LOGO_LINUX_MONO
  • CONFIG_LOGO_LINUX_VGA16
  • CONFIG_LOGO_LINUX_CLUT224

Rootfs

File System will be generated with Debian script or Ubuntu script (mkdebian_stretch.sh/mkubuntu_BionicBeaver.sh)

Applications

Applications will be generated with Debian script or Ubuntu script (mkdebian_stretch.sh/mkubuntu_BionicBeaver.sh)

Additional Software

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Note:
  • Add description for other Software, for example SI CLK Builder ...
  • SI5338 and SI5345 also Link to:

SI5338

File location <design name>/misc/Si5338/Si5338-*.slabtimeproj

General documentation how you work with these project will be available on Si5338

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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anchorTable_dch
titleDocument change history.

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DateDocument Revision

Authors

Description

Page info
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modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
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Page info
infoTypeModified by
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  • fix brocken links
2020-03-30v.5Mohsen Chamanbaz
  • 2019.2 release
--all

Page info
infoTypeModified users
dateFormatyyyy-MM-dd
typeFlat

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Legal Notices

Include Page
IN:Legal Notices
IN:Legal Notices

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