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Template Revision 2.4 7 - on construction

Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"

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DateVivadoProject BuiltAuthorsDescription
2020-01-222019.2TE0712-test_board_noprebuilt-vivado_2019.2-build_3_20200122155446.zip
TE0712-test_board-vivado_2019.2-build_3_20200122155355.zip
John Hartfiel
  • update for linux user
  • new script features
2020-01-082019.2TE0712-test_board_noprebuilt-vivado_2019.2-build_2_20200108161124.zip
TE0712-test_board-vivado_2019.2-build_2_20200108155510.zip
John Hartfiel
  • 2019.2 update
  • Vitis support
2019-04-182018.3TE0712-test_board_noprebuilt-vivado_2018.3-build_05_20190418082456.zip
TE0712-test_board-vivado_2018.3-build_05_20190418082240.zip
John Hartfiel
  • MCU depends on EOS now
2019-02-222018.3TE0712-test_board_noprebuilt-vivado_2018.3-build_01_20190222073819.zip
TE0712-test_board-vivado_2018.3-build_01_20190222073754.zip
John Hartfiel
  • TE Script update
  • linux changes
  • SCU rework
  • SI5338 CLKBuilder Pro Project
2018-09-052018.2te0712-test_board-vivado_2018.2-build_03_20180906071356.zip
te0712-test_board_noprebuilt-vivado_2018.2-build_03_20180906071434.zip
John Hartfiel
  • chance block design: qspi clks, clock wizard(REV01 only)
  • change timing constrains
  • add hello_te0712 application
  • new SREC bootloader version
  • change linux device tree
2018-05-252017.4te0712-test_board-vivado_2017.4-build_10_20180525155402.zip
te0712-test_board_noprebuilt-vivado_2017.4-build_10_20180525155555.zip
John Hartfiel
  • solved eth issue for REV01
  • changed design + second design for REV01
2018-04-122017.4te0712-test_board-vivado_2017.4-build_07_20180412081225.zip
te0712-test_board_noprebuilt-vivado_2017.4-build_07_20180412081253.zip
John Hartfiel
  • bugfix constrain file - ETH REFCLK, timing
2018-03-282017.4te0712-test_board-vivado_2017.4-build_07_20180328145151.zip
te0712-test_board_noprebuilt-vivado_2017.4-build_07_20180328145135.zip
John Hartfiel
  • new assembly variant
2018-01-082017.4te0712-test_board-vivado_2017.4-build_02_20180108155712.zip
te0712-test_board_noprebuilt-vivado_2017.4-build_02_20180108155735.zip
John Hartfiel
  • no design changes
  • small constrain changes
2017-12-152017.2te0712-test_board-vivado_2017.2-build_07_20171215172447.zip
te0712-test_board_noprebuilt-vivado_2017.2-build_07_20171215172514.zip
John Hartfiel
  • add SI5338 initialisation with MCS
  • add Ethernet IP
2017-11-072017.2te0712-test_board-vivado_2017.2-build_05_20171107172917.zip
te0712-test_board_noprebuilt-vivado_2017.2-build_05_20171107172939.zip
John Hartfiel
  • add wiki link in Boart Part Files
  • set correct short link for te0712-02-200-2c
2017-10-052017.2te0712-test_board-vivado_2017.2-build_03_20171005082148.zip
te0712-test_board_noprebuilt-vivado_2017.2-build_03_20171005082225.zip
John Hartfiel
  • initial release


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Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

Get prebuilt boot binaries

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select Create and open delivery binary folder
      Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated

QSPI

  1. Connect JTAG and power on Connect JTAG and power on PCB
  2. (if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
  3. Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
    Note: Alternative use SDK or setup Flash on Vivado manually
              optional "TE::pr_program_flash_binfile -swapp hello_te0712" possible
  4. Reboot (if not done automatically)

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For SDK project creation, follow instructions from:

Vitis

Application

Template location: ./sw_lib/sw_apps/

scu

MCS Firmware to configure SI5338 and Reset System.

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----------------------------------------------------------

FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2019.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

  • Modified Files: blconfig.h, bootloader.c
  • Changes:
    • Add some console outputs and changed bootloader read address.
    • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2019.2 xilisf_v5_11

  • Changed default Flash type to 5.

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Zynq Example:

zynq_fsbl

TE modified 2019.2 FSBL

General:

  • Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot  platform-top.h)
    • CPLD access
    • Read CPLD Firmware and SoC Type
    • Configure Marvell PHY

zynq_fsbl_flash

TE modified 2019.2 FSBL

General:

  • Modified Files: main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

ZynqMP Example:

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zynqmp_fsbl

TE modified 2019.2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
  • Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2019.2 FSBL

General:

  • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation


zynqmp_pmufw

Xilinx default PMU firmware.

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General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Template location: ./sw_lib/sw_apps/

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2019.2 SREC

Bootloader to load app or second bootloader from flash into DDR

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Hello TE0712 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate u-boot.srec. Vivado to generate *.mcs

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Change platform-top.h:

Code Block
languagejs

#include <configs/platform-auto.h>

#define CONFIG_SYS_BOOTM_LEN 0xF000000

Device Tree

Code Block
languagejs
/include/ "system-conf.dtsi"
/ {
};

/* QSPI PHY */

&axi_quad_spi_0 {
    #address-cells = <1>;
    #size-cells = <0>;
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        spi-tx-bus-width=<1>;
        spi-rx-bus-width=<4>;
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
        spi-max-frequency = <25000000>;
    };
};


/* ETH PHY */
&axi_ethernetlite_0 {
    phy-handle = <&phy0>;
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy0: phy@0 {
            device_type = "ethernet-phy";
            reg = <1>;
        };
    };
};


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DateDocument RevisionAuthorsDescription

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modified-date
modified-date
dateFormatyyyy-MM-dd

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current-version
current-version
prefixv.

Page info
infoTypeModified by
typeFlat

  • update scripts, new features and linux support
2020-01-08v.33John Hartfiel
  • 2019.2 release
2019-04-18v.32John Hartfiel
  • small design changes
2019-02-22

v.31

John Hartfiel
  • 2018.3 release (include design reworks)

2018-09-06

v.30John Hartfiel
  • 2018.2 release

2018-05-25

v.28John Hartfiel
  • Design update

2018-05-08

v.27John Hartfiel
  • Know Issues
  • Documentation

2018-04-12

v.23John Hartfiel
  • Design Update

2018-03-28

v.22John Hartfiel
  • Know Issue for PCB REV01 only
  • Fix typo
  • New assembly variant
2018-02-13v.19John Hartfiel
  • Release 2017.4
2018-01-08v.16John Hartfiel
  • Add SCU source path
2017-12-15v.15John Hartfiel
  • Update Design and Description
2017-11-07v.11John Hartfiel
  • Update Design Files
2017-10-06v.10John Hartfiel
  • small Document Update
2017-10-05

v.8

John Hartfiel
  • Release 2017.2
2017-09-11v.1

Page info
created-user
created-user

  • Initial release
---All

Page info
modified-users
modified-users

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