- Created by Waldemar Hanemann, last modified by John Hartfiel on 18 04, 2024
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Overview
Refer to http://trenz.org/teg2000-info for the current online version of this manual and other available documentation.
This page describes briefly how to generate the fpga configuration file (Bitstream/cfg file) from the blink-example and how to program the FPGA. For a more detailed description of the tools follow the Quick start section of colognechip ug1002.
Key Features
- USB(JTAG/UART)
- LED
Revision History
Date | Project Built | Authors | Description |
---|---|---|---|
2024-04-15 | TEG2000-test-board-cc-toolchain-win-trenz_20240415.zip | Waldemar Hanemann |
|
Release Notes and Know Issues
Issues | Description | Workaround | To be fixed version |
---|---|---|---|
No known issues | --- | --- | --- |
Requirements
Software
Software | Version | Note |
---|---|---|
Yosys | 0.37+39 | needed for RTL synthesis |
GateMate EasyConvert Place&Route | 2024.02-001 | needed for implementation |
openFPGALoader | v.0.11.0 | needed for loading bitstream into FPGA |
Hardware
Design supports following modules:
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
---|---|---|---|---|---|---|---|
TEG2000-01-P001* | -- | REV01 | -- | 16MB | -- |
*used as reference
Design supports following carriers:
Carrier Model | Notes |
---|---|
TE0703* | We only support TE0703 up until now. |
*used as reference
Content
Design Sources
Type | Location | Notes |
---|---|---|
Toolchain | <project folder>\bin | script-based tools for synthesis, implementation, bitfile generation and programming |
fpga project | <project folder>\workspace\blink\log <project folder>\workspace\blink\net <project folder>\workspace\blink\sim <project folder>\workspace\blink\src | .bat scripts can be used for synthesis & implementation & programming |
Prebuilt
File | File-Extension | Description |
---|---|---|
Constraint-File | *.ccf | FPGA pin constraint for pin-location, naming, input-output setting etc. |
Design source-files | *.v , *.vhd | hdl design files describing the fpga functional description and I/O signals |
Config File | *.cfg | Config File Data for FPGA. Comments included. |
BIT-File | *.bit | FPGA (PL Part) Configuration File |
Download
Reference Design is available on:
It contains the tools, the example project blink and several other sample projects(those are not documented here).
Design Flow & Launch
- After downloading the test design go into the directory <project folder>\workspace\blink\
- On Windows you can now run the *.bat scripts.
- Run synth.bat
- Run impl.bat
- Connect the Board (TEG2000 + TE0703 carrier) to power and USB, see Getting started.
- Run flash.bat to program the on-board qspi flash
- Press reset, the green LED D2 should be blinking
System Design
HDL Sources
The design source files exist in verilog and in vhdl.
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity blink is port ( clk : in std_logic; rst : in std_logic; led : out std_logic ); end entity; architecture rtl of blink is component CC_PLL is generic ( REF_CLK : string; -- reference input in MHz OUT_CLK : string; -- pll output frequency in MHz PERF_MD : string; -- LOWPOWER, ECONOMY, SPEED LOW_JITTER : integer; -- 0: disable, 1: enable low jitter mode CI_FILTER_CONST : integer; -- optional CI filter constant CP_FILTER_CONST : integer -- optional CP filter constant ); port ( CLK_REF : in std_logic; USR_CLK_REF : in std_logic; CLK_FEEDBACK : in std_logic; USR_LOCKED_STDY_RST : in std_logic; USR_PLL_LOCKED_STDY : out std_logic; USR_PLL_LOCKED : out std_logic; CLK0 : out std_logic; CLK90 : out std_logic; CLK180 : out std_logic; CLK270 : out std_logic; CLK_REF_OUT : out std_logic ); end component; signal clk0 : std_logic; signal counter : unsigned(26 downto 0); begin socket_pll : CC_PLL generic map ( REF_CLK => "10.0", OUT_CLK => "100.0", PERF_MD => "ECONOMY", LOW_JITTER => 1, CI_FILTER_CONST => 2, CP_FILTER_CONST => 4 ) port map ( CLK_REF => clk, USR_CLK_REF => '0', CLK_FEEDBACK => '0', USR_LOCKED_STDY_RST => '0', USR_PLL_LOCKED_STDY => open, USR_PLL_LOCKED => open, CLK0 => clk0, CLK90 => open, CLK180 => open, CLK270 => open, CLK_REF_OUT => open ); process(clk0) begin if rising_edge(clk0) then if rst = '0' then counter <= (others => '0'); else counter <= counter + 1; end if; end if; end process; led <= counter(26); end architecture;
Constraints
Basic module constraints
## blink.ccf # # Date: 2022-10-21 # # Format: # <pin-direction> "<pin-name>" Loc = "<pin-location>" | <opt.-constraints>; # # Additional constraints can be appended using the pipe symbol. # Files are read line by line. Text after the hash symbol is ignored. # # Available pin directions: # # Pin_in # defines an input pin # Pin_out # defines an output pin # Pin_inout # defines a bidirectional pin # # Available pin constraints: # # SCHMITT_TRIGGER={true,false} # enables or disables schmitt trigger (hysteresis) option # PULLUP={true,false} # enables or disables I/O pullup resistor of nominal 50kOhm # PULLDOWN={true,false} # enables or disables I/O pulldown resistor of nominal 50kOhm # KEEPER={true,false} # enables or disables I/O keeper option # SLEW={slow,fast} # sets slew rate to slow or fast # DRIVE={3,6,9,12} # sets output drive strength to 3mA..12mA # DELAY_OBF={0..15} # adds an additional delay of n * nominal 50ps to output signal # DELAY_IBF={0..15} # adds an additional delay of n * nominal 50ps to input signal # FF_IBF={true,false} # enables or disables placing of FF in input buffer, if possible # FF_OBF={true,false} # enables or disables placing of FF in output buffer, if possible # LVDS_BOOST={true,false} # enables increased LVDS output current of 6.4mA (default: 3.2mA) # LVDS_TERM={true,false} # enables on-chip LVDS termination resistor of nominal 100Ohm, in output mode only # # Global IO constraints can be set with the default_GPIO statement. It can be # overwritten by individual settings for specific GPIOs, e.g.: # default_GPIO | DRIVE=3; # sets all output strengths to 3mA, unless overwritten # Pin_in "clk" Loc = "IO_SB_A8" | SCHMITT_TRIGGER=true; Pin_in "rst" Loc = "IO_EB_B0"; # SW3 Pin_out "led" Loc = "IO_SB_B4"; # D1
Additional Software
No additional software is needed.
App. A: Change History and Legal Notices
Document Change History
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Date | Document Revision | Authors | Description |
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2024-04-16 | v.13 | Waldemar Hanemann |
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Legal Notices
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Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy
Document Warranty
The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.
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In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.
Copyright Notice
No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.
Technology Licenses
The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.
Environmental Protection
To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.
REACH, RoHS and WEEE
REACH
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RoHS
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WEEE
Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).
Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.
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