You are viewing an old version of this page. View the current version.

Compare with Current View Page History

« Previous Version 3 Next »


Overview


CPLD Device with designator U46: 10M08SAU169

Feature Summary

  • something to have access to CPLD to read out status of Power management
  • Power management
  • Reset

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification


Port Description

Name / opt. VHD NameDirectionPinPullup/DownBank Power

Description


PCB REV04 REV05 Connection

PCB REV01 REV02 Connection

JTAGEN
inE5--3.3Vfixed to 3.3V
TCK_MAX10inG2--3.3VJTAG 
TMS_MAX10inG1--3.3VJTAG
TDO_MAX10outF6--3.3VJTAG 
TDI_MAX10inF5--3.3VJTAG 
RST_EN      inout27NONE3.3VIN

Reset pin output to reset FPGA via CPLD chip

 


EN_VTT_PL_DDRoutJ2
3.3V LVCMOS


EN_2V5_PL_DDRoutJ1
3.3V LVCMOS
EN_1V2_PL_DDRoutH4
3.3V LVCMOS
PG_1V2_PL_DDR
H5
3.3V LVCMOS
EN_1V8_PS_AUXoutM2
3.3V LVCMOS
PG_SOMoutM1
3.3V LVCMOS

This pin is used as power good (input)

PG_VCCINT
N3
3.3V LVCMOS
LTM_FAULT
N2
3.3V LVCMOS
SC_EXT_2outL3
3.3V LVCMOS
M_SDA
M3
3.3V LVCMOS
MRoutK2
3.3V LVCMOS
EN_SOM
K1
3.3V LVCMOS
SC_EXT_3
L2
3.3V LVCMOS






SMB_ALERTn
 L4
3.3V LVCMOS
PG_2V5_PL_DDR
 L5
3.3V LVCMOS
EN_LTM_RUNPout
M5
3.3V LVCMOS
M_SCL M4
3.3V LVCMOS
nRST_SYS K5
3.3V LVCMOS
EN_0V9_GTH_AVCCout
N5
3.3V LVCMOS
EN_0V9_GTY_AVCCout
N4
3.3V LVCMOS

PG_1V2_PS_DDR

 M7
3.3V LVCMOS

PG_0V9_GTH_AVCC

 N6
3.3V LVCMOS

PG_0V9_GTY_AVCC

 N8
3.3V LVCMOS
EN_3V3_SWout
N7
3.3V LVCMOS
EN_1V2_PS_PLLout
J6
3.3V LVCMOS

PG_1V8_PS_GTR_AVTT

 M9
3.3V LVCMOS

PG_1V8

 M8
3.3V LVCMOS
EN_2V5_PS_DDRout
M13
3.3V LVCMOS
PG_1V2_GTY_AVTT N9
3.3V LVCMOS
EN_1V2_GTY_AVTTout
N10
3.3V LVCMOS
M_INT L11
3.3V LVCMOS
EN_1V8_VCC_ADCout
M11
3.3V LVCMOS
PG_1V8_PS_GTR_AVCC K8
3.3V LVCMOS
EN_VTT_PS_DDRout
J8
3.3V LVCMOS
EN_1V8out
L10
3.3V LVCMOS
EN_1V8_GTY_AUXout
M10
3.3V LVCMOS
PG_2V3 N12
3.3V LVCMOS

 






EN_+1.8V_GTR_AVTT_PS

out
 K10
3.3V LVCMOS

EN_+1.8V_GTH_AUX

out
 K11
3.3V LVCMOS

EN_+1.8V_AUX

out
K12
3.3V LVCMOS

EN_+1.2V_GTH_AVTT

out
J12
3.3V LVCMOS

+3.3V_SW


J9
3.3V LVCMOS

EN_+1.2V_PS_DDR

out
J13
3.3V LVCMOS

EN_+0.85V_GTR_AVCC_PS

out
H13
3.3V LVCMOS

PG_+1.2V_GTH_AVTT


H9
3.3V LVCMOS

EN_VCCINT

out
H8
3.3V LVCMOS

EN_+2.3V

out
G13
3.3V LVCMOS

PG_+1.8V_AUX


G12
3.3V LVCMOS

PG_2.5V_PS_DDR


L13
3.3V LVCMOS

Functional Description

Power

All power regulators are controlled by the power sequencer core. It enables and discharges the power regulators and monitors the power good signals.

The power-up sequence corresponds to Intel's recommendations and is shown in the table below:

Power GroupPower enablePower goodNotes
0

EN_0V9

PG_0V9

--

1

EN_0V95

PG_0V95

--

2EN_1V8PG_1V8--
3

EN_1V8VIO

PG_1V8VIO

--

EN_1V35

PG_1V35

--

EN_VTT

--

--

VADJ_EN

PG_VADJ

1.8V (default)

MAX_IO19

MAX_IO20

B2B J2-74/J2-76 / Signals for 3.3V on carrier board TEIB0006 → EN_3V3MB/PG_MB_3.3V

MAX_IO23

MAX_IO22

B2B J2-86/J2-82 / Signals for 1.8V on carrier board TEIB0006 → EN_1V8MB/PG_MB_1.8V
(required for VCCIO voltage at Bank 2J/2K)

The voltages for Bank 2K ( VCCIO2K) and Bank 2J (VCCIO2J) are supplied externally via the B2B connectors (J1-53/53 and J2-29/30).

Output voltage VADJ of power regulator U11 is set to 1.8V via VADJ_VS0 and VADJ_VS1 pin. Possible selectable voltages are 1.8V, 2.5V and 3.0V.

I2C interface

CPLD firmware consists of a i2c t GPIO block. This subsystem provides i2c protocol interface to  32-bit (4 x 8-bit) (GPIO_input[31:0]) registers for reading from CPLD and (4 x 8-bit) (GPIO_output[31:0]) registers for writing in CPLD as general purpose parallel input and output (I/Os). The written and read data is communicated from/to FPGA via i2c bus interface protocol. The address of this block in the firmware is 0x20.In this case related i2c bus is bus 1. 



RegisterDirection in CPLDAddress
GPIO_input[7:0]Output (reading from CPLD)0x00
GPIO_input[15:8]Output (reading from CPLD)0x01
GPIO_input[23:16]Output (reading from CPLD)0x02
GPIO_input[31:24]Output (reading from CPLD)0x03
GPIO_output[7:0]Input (writing to CPLD)0x00
GPIO_output[15:8]Input (writing to CPLD)0x01
GPIO_output[23:16]Input (writing to CPLD)0x02
GPIO_output[31:24]Input (writing to CPLD)0x03

NOSEQ pin

This pin in PCB REV04 with old CPLD firmware version (REV04) is  used as boot mode pin select. If  CPLD is programmed with SC0820_qspi_sd_jtag.jed as jed file and  NOSEQ is  high, JTAG boot mode will be selected. For PCB REV05 or PCB REV04 with new CPLD firmware (CPLD firmware REV05) NOSEQ pin can be used by user as GPIO pin and accessed via i2c interface. In this case the following table can be used:

NOSEQ pin as outputConditionCommand in linux console
'1'GPIO_output(16) = '1'
i2cset -y 1 0x20 0x02 0x01
'0'GPIO_output(16) = '0'
i2cset -y 1 0x20 0x02 0x00
NOSEQ pin as inputDescriptionCommand in linux console
Reading state of NOSEQ pinGPIO_input(16) = NOSEQ
i2cget -y 1 0x20 0x02


Access to CPLD Registers

CPLD registers can be accessed via i2c interface. In the following table is shown how these registers can be read or written:

RegisterDirection in CPLDAddressRelated instruction in linux console to access the register
GPIO_input[7:0]Output (reading from CPLD)0x00i2cget -y 1 0x20 0x00
GPIO_input[15:8]Output (reading from CPLD)0x01i2cget -y 1 0x20 0x01
GPIO_input[23:16]Output (reading from CPLD)0x02i2cget -y 1 0x20 0x02
GPIO_input[31:24]Output (reading from CPLD)0x03i2cget -y 1 0x20 0x03
GPIO_output[7:0]Input (writing to CPLD)0x00i2cset -y 1 0x20 0x00 <data>
GPIO_output[15:8]Input (writing to CPLD)0x01i2cset -y 1 0x20 0x01 <data>
GPIO_output[23:16]Input (writing to CPLD)0x02i2cset -y 1 0x20 0x02 <data>
GPIO_output[31:24]Input (writing to CPLD)0x03

i2cset -y 1 0x20 0x03 <data>

Some of these registers are using to show some information same as  CPLD revision and boot mode while booting.

RegisterAddressrelated  dataRead/write by userDescription
GPIO_input[7:0]0x00CPLD REVISION (8 bits)No
GPIO_input[15:8]0x01"00" & BOOTMODE_GEN (2 bits) &  PUDC (1 bit) & CPLD_BM (1 bit) & BOOT_MODE (2 bits)No

BOOTMODE_GEN is a generic parameter in firmware code to select type of jed-file. For example if this parameter is 3 , then by programming the related jed-file the user can have all boot mode options. (QSPI/JTAG/SD Card/eMMC).

PUDC is the state of PUDC pin of FPGA.

CPLD_BM is a parameter to show if boot mode selection is executed via hardware ( if low) or software (if high)

BOOT_MODE shows selected boot mode.

GPIO_input8[16]0x02NOSEQ pinYes
RegisterAddressrelated data
Description
GPIO_output[16]0x02NOSEQ pinYes

If CPLD firmware version is  REV05, then boot mode, CPLD revision and some features of the board will be displayed in the linux console via FSBL code  while booting. The format of these informations are shown in the following:

InformationDisplayed in Linux consoleDescription
CPLD RevisionCPLD_REV = <cpld revision>
Boot mode selection procedureCPLD_BM = < bm selection procedure>
  • If boot mode via hardware is selected → Deactive(0)
  • If boot mode via software (in linux console or via FSBL code) is selected → Active(1)
Jed file that on CPLD is programmedBOOTMODE_GEN = < jed file type>
  • Jed file type can be one of the following types :
    • (0) QSPI/SD
    • (1) QSPI/JTAG
    • (2) JTAG/SD
    • (3) default QSPI/JTAG/SD/eMMC
PUDC pin statePUDC_MODE = <pudc state>
  • PUDC can have one of the following state:
    • Pull-up activated (0)
    • Pull-up deactivated (1)
Boot modeBOOT_MODE = <boot mode>
  • The following boot modes can displayed:
    • eMMC (0)
    • JTAG (1)
    • QSPI (2)
    • SD Card (3)

The CPLD revision, boot mode and other informations will be displayed while booting as shown:

All information while booting

If PCB revision is REV04 and  CPLD firmware version is older than REV05 (for example REV04) , then it will not be displayed these informations same as  boot mode while booting and the following message will be displayed:

Message while booting if CPLD firmware version is old for PCB REV04


Appx. A: Change History

For PCB REV01 and REV02 Documentation available on: TE0820-REV01_REV02 CPLD

Revision Changes

  • REV02 to REV03
    • changed top design from block design to text design
  • REV01 to REV02
    • added Pin L3 SC_EXT_2 as output and set to VCC to enable USB

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

Error rendering macro 'page-info'

Ambiguous method overloading for method jdk.proxy244.$Proxy3575#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]

Error rendering macro 'page-info'

Ambiguous method overloading for method jdk.proxy244.$Proxy3575#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]

REV05REV04,REV05

Error rendering macro 'page-info'

Ambiguous method overloading for method jdk.proxy244.$Proxy3575#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]


  • add LED Designator Note

All

Error rendering macro 'page-info'

Ambiguous method overloading for method jdk.proxy244.$Proxy3575#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]


Appx. B: Legal Notices

Data Privacy

Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

Limitation of Liability

In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.

Copyright Notice

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.

Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.


Error rendering macro 'page-info'

Ambiguous method overloading for method jdk.proxy244.$Proxy3575#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]



Table of contents

  • No labels