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Trenz Electronic TE0728 is an automotive-grade FPGA module integrating a Xilinx Automotive Zynq-7020 FPGA, two 100 Mbit Ethernet transceivers (PHY) , 512 MByte DDR3L SDRAM, 16 MByte Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips.
Within the complete module only Automotive components are installed.
All this in a compact 6 x 6 cm form factor, at the most competitive price.
Refer to http://trenz.org/te0728-info for the current online version of this manual and other available documentation.
There is no hardware component to be programmed on teh carrier.
Storage device name | Content | Notes |
---|---|---|
Signal | Designator | B2B | Signal Level | Boot Mode |
---|---|---|---|---|
Boot_R | J4 | J2-11 | Open | QSPI |
Short | SD Card |
There is a user push button which is used for RESET signal.
Signal | Designator | B2B | Active Level |
---|---|---|---|
RESET | S1 | J2-7 | Active High |
FPGA bank number and number of I/O signals connected to the B2B connector:
B2B Connector | Interfaces | Number of I/O | Notes |
---|---|---|---|
J1 | User I/O | 48 singel ended, 24 differential | Connected to Bank 13 |
4 Single ended | MIO10-13 | ||
CANH , CANL | 2 single ended | MIO8, MIO9 | |
J2 | User I/O | 22 singel ended, 11 differential | |
38 single ended | MIO16-53 | ||
SoM Control Signals | 5 | RESET, RST_OUT, BOOT_R, | |
JTAG Interface | 4 | TCK , TDO, TDI, TMS | |
J3 | User I/O | 20 Single ended, 10 differential | Connected to Bank 35 |
34 single ended, 17 differential | Connected to Bankd 33 | ||
Ethernet 1 | 4 single ended, 2 differential | ETH_CTREF , ETH_TD+, ETH_TD- , ETH_RD+, ETH_RD-, ETH_LED1, ETH_LED2, ETH_LED3 | |
Ethernet 2 | 4 single ended, 2 differential | ETH_CTREF , ETH_TD+, ETH_TD- , ETH_RD+, ETH_RD-, ETH_LED1, ETH_LED2, ETH_LED3 |
B2B Connector | Interfaces | Number of I/O | Notes |
---|---|---|---|
J5 | User I/O | 48 singel ended, 24 differential | Connected to Bank 13 |
34 single ended, 17 differential | Connected to Bank 33 | ||
J6 | User I/O | 42 singel ended, 21 differential | |
27 single ended | MIO16-39 + MIO 51-53 | ||
4 single ended | MIO10-13 | ||
SoM Control Signals | 3 | RESET, RST_OUT, BOOT_R | |
JTAG Interface | 4 | TCK , TDO, TDI, TMS | |
CANH , CANL | 2 Single ended | MIO8 , MIO9 |
JTAG access to the Xilinx XXXXXXX FPGA through B2B connector JM2.
JTAG Signal | B2B Pin |
---|---|
TMS | J2-12 |
TDI | J2-10 |
TDO | J2-8 |
TCK | J2-6 |
Chip/Interface | IC | PS7 Peripheral | Notes |
---|---|---|---|
On-board QSPI flash memory S25FL127SABMFV10 is used to store initial FPGA configuration. Datasheet is provided in Texas Instruments. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500.
MIO Pin | Schematic | U13 Pin | Notes |
---|---|---|---|
MIO Pin | Schematic | U7 Pin | Notes |
---|---|---|---|
SDA | |||
SCL |
MIO Pin | Schematic | Uxx Pin | Notes |
---|---|---|---|
SDA | |||
SCL |
Schematic | Color | Connected to | Active Level | IO Standard |
---|---|---|---|---|
The TE0728 SoM has XXX GByte volatile DDR3 SDRAM IC for storing user application code and data.
Schematic | ETH1 | ETH2 | Pullup | Notes |
---|---|---|---|---|
CTREF | ||||
TD+ | ||||
TD- | ||||
RD+ | ||||
RD- | ||||
LED1 | ||||
LED2 | ||||
LED3 | ||||
POWERDOWN/INT | ||||
RESET_N |
MIO Pin | Schematic | U16 Pin | Notes |
---|---|---|---|
D | |||
R |
IC | Description | Frequency | Used as |
---|---|---|---|
MEMS Oscillator | MHz | ||
MEMS Oscillator | MHz | ||
RTC (internal oscillator) | KHz |
Power supply with minimum current capability of 3.5 A for system startup is recommended.
Power Input Pin | Typical Current |
---|---|
VIN | TBD* |
* TBD - To Be Determined
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Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
---|---|---|---|---|---|
Bank | Schematic Name | Voltage | Notes |
---|---|---|---|
6 x 6 modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.
3 x REF-189018-01 (compatible to SEM-140-02-03.0-H-D-A), (80 pins, "40" per row)
Operating Temperature:-55°C ~ 125°C
Current Rating: 2.6A per ContactNumber of Positions: 80
Number of Rows: 2
Symbols | Description | Min | Max | Unit |
---|---|---|---|---|
VCCPINT | PS internal logic supply voltage | -0.5 | 1.1 | V |
VCCPAUX | PS auxiliary supply voltage | -0.5 | 2.0 | V |
VCCPLL | PS PLL supply | -0.5 | 2.0 | V |
VCCO_DDR | PS DDR I/O supply voltage | -0.5 | 2.0 | V |
VPREF | PS input reference voltage | -0.5 | 2.0 | V |
VCCO_MIO0 | PS MIO I/O supply voltage for HR I/O banks | -0.5 | 3.6 | V |
VCCO_MIO1 | PS MIO I/O supply voltage for HR I/O banks | 1.71 | 3.45 | V |
Symbols | Description | Min | Max | Unit |
---|---|---|---|---|
VCCINT | PL internal logic supply voltage | -0.5 | 1.1 | V |
VCCPAUX | PL auxiliary supply voltage | -0.5 | 2.0 | V |
VCCPLL | PL PLL supply | -0.5 | 1.1 | V |
VPREF | PL input reference voltage | -0.5 | 2.0 | V |
VCCO | PL supply voltage for HR I/O banks | -0.5 | 3.6 | V |
VIN | I/O input voltage for HR I/O banks | 1.71 | 3.45 | V |
Technical Specifications
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
VIN supply voltage | 3.5 | 60 | V | TPS54260-Q1 datasheets. |
Supply voltage for PS MIO banks | 1.71 | 3.465 | V | See Xilinx DS187 datasheet. |
I/O input voltage for PS MIO banks | -0.2 | VCCO_MIO + 0.20 | V | See Xilinx DS187 datasheet. |
Supply voltage for PS DDR | 1.14 | 1.89 | V | See Xilinx DS187 datasheet. |
I/O input voltage for PS DDR | -0.20 | VCCO_DDR + 0.20 | V | See Xilinx DS187 datasheet. |
Supply voltage for HR I/Os banks | 1.14 | 3.465 | V | See Xilinx DS187 datasheet. |
I/O input voltage for HR I/O banks | -0.20 | VCCIO + 0.20 | V | See Xilinx DS187 datasheet. |
Storage Temperature | -40 | 125 | °C | See Xilinx DS187 datasheet. |
Commercial grade: 0°C to +70°C.
Industrial and automotive grade: -40°C to +85°C.
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
VIN supply voltage | 3.5 | 60 | V | TPS54260-Q1 datasheets. |
Supply voltage for PS MIO banks | 1.71 | 3.465 | V | See Xilinx DS187 datasheet. |
I/O input voltage for PS MIO banks | -0.2 | VCCO_MIO + 0.20 | V | See Xilinx DS187 datasheet. |
Supply voltage for PS DDR | 1.14 | 1.89 | V | See Xilinx DS187 datasheet. |
I/O input voltage for PS DDR | -0.20 | VCCO_DDR + 0.20 | V | See Xilinx DS187 datasheet. |
Supply voltage for HR I/Os banks | 1.14 | 3.465 | V | See Xilinx DS187 datasheet. |
I/O input voltage for HR I/O banks | -0.20 | VCCIO + 0.20 | V | See Xilinx DS187 datasheet. |
Storage Temperature | -65 | 150 | °C | See Xilinx DS187 datasheet. |
CAN Transceiver Temperature | -40 | 125 | °C | See Texas Instrument sn65hvd230q-q1 datasheet. |
SPI Flash Memory | -40 | 85 | °C | See Cypress S25FL127S datasheet. |
DDR3 SDRAM Temperature | -40 | 95 | °C | See Nanya NT5CC256M16CP-DIA datasheet. |
Physical Dimensions
Module size: 60 mm × 60 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 7 mm.
PCB thickness: 1.6 mm.
Trenz shop TE0728 overview page | |
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English page | German page |
Date | Revision | Note | PCN | Documentation Link |
---|---|---|---|---|
- | 01 | Prototypes | - | - |
Hardware revision number is printed on the PCB board next to the module model number separated by the dash.
Date | Revision | Contributor | Description |
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-- | all |
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