Table of contents
Overview
Key Features
- PetaLinux
- MicroBlaze
- SREC
- I2C
- Flash
- MIG
- FMeter
- SI5338 initialisation with MCS
- ETH
Revision History
Date | Vivado | Project Built | Authors | Description |
---|---|---|---|---|
2018-09-05 | 2018.2 | John Hartfiel |
| |
2018-05-25 | 2017.4 | te0712-test_board-vivado_2017.4-build_10_20180525155402.zip te0712-test_board_noprebuilt-vivado_2017.4-build_10_20180525155555.zip | John Hartfiel |
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2018-04-12 | 2017.4 | te0712-test_board-vivado_2017.4-build_07_20180412081225.zip te0712-test_board_noprebuilt-vivado_2017.4-build_07_20180412081253.zip | John Hartfiel |
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2018-03-28 | 2017.4 | te0712-test_board-vivado_2017.4-build_07_20180328145151.zip te0712-test_board_noprebuilt-vivado_2017.4-build_07_20180328145135.zip | John Hartfiel |
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2018-01-08 | 2017.4 | te0712-test_board-vivado_2017.4-build_02_20180108155712.zip te0712-test_board_noprebuilt-vivado_2017.4-build_02_20180108155735.zip | John Hartfiel |
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2017-12-15 | 2017.2 | te0712-test_board-vivado_2017.2-build_07_20171215172447.zip te0712-test_board_noprebuilt-vivado_2017.2-build_07_20171215172514.zip | John Hartfiel |
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2017-11-07 | 2017.2 | te0712-test_board-vivado_2017.2-build_05_20171107172917.zip te0712-test_board_noprebuilt-vivado_2017.2-build_05_20171107172939.zip | John Hartfiel |
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2017-10-05 | 2017.2 | te0712-test_board-vivado_2017.2-build_03_20171005082148.zip te0712-test_board_noprebuilt-vivado_2017.2-build_03_20171005082225.zip | John Hartfiel |
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Release Notes and Know Issues
Issues | Description | Workaround | To be fixed version |
---|---|---|---|
For PCB REV01 only: prebuilt does not boot | There is a Pullup missing on REV01 I2C SCL, so SI5338 configuration over MCS fails | Remove MCS | solved with 20180528 update |
For PCB REV01 only: CLK1B is not available on | additional clk is not connected on PCB | use other internal generated CLK, maybe more effort is needed to get ETH running | solved with 20180528 update |
SREC SPI BootLoader default Offset | Default load offset is set to 0x400000 | Change manually on SDK to 0x5E0000 | solved with 20180412 update |
Requirements
Software
Software | Version | Note |
---|---|---|
Vivado | 2018.2 | needed |
SDK | 2018.2 | needed |
PetaLinux | 2018.2 | needed |
Hardware
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | Others | Notes |
---|---|---|---|---|---|---|
te0712-01-100-1i | 01_100_1i | REV01 | 1GB | 32MB | ||
te0712-01-100-2c | 01_100_2c | REV01 | 1GB | 32MB | ||
te0712-01-100-2c3 | 01_100_2c | REV01 | 1GB | 32MB | 2,5 mm connector | |
te0712-01-200-1i | 01_200_1i | REV01 | 1GB | 32MB | ||
te0712-01-200-2i | 01_200_2i | REV01 | 1GB | 32MB | ||
te0712-01-200-2c | 01_200_2c | REV01 | 1GB | 32MB | ||
te0712-01-200-2c3 | 01_200_2c | REV01 | 1GB | 32MB | 2,5 mm connector | |
te0712-02-35-2i | 35_2i | REV02 | 1GB | 32MB | ||
te0712-02-100-1i | 100_1i | REV02 | 1GB | 32MB | ||
te0712-02-100-2c | 100_2c | REV02 | 1GB | 32MB | ||
te0712-02-100-2c3 | 100_2c | REV02 | 1GB | 32MB | 2,5 mm connector | |
te0712-02-100-2ca | 100_2ca | REV02 | 1GB | 32MB | Micron QSPI Flash | |
te0712-02-200-1i | 200_1i | REV02 | 1GB | 32MB | ||
te0712-02-200-1i3 | 200_1i | REV02 | 1GB | 32MB | 2,5 mm connector | |
te0712-02-200-2i | 200_2i | REV02 | 1GB | 32MB | ||
te0712-02-200-2c | 200_2c | REV02 | 1GB | 32MB | ||
te0712-02-200-2c3 | 200_2c | REV02 | 1GB | 32MB | 2,5 mm connector |
Design supports following carriers:
Carrier Model | Notes |
---|---|
TE0701 | |
TE0703 | used as reference carrier |
TE0705 | |
TE0706 | |
TEBA0841 |
Additional HW Requirements:
Additional Hardware | Notes |
---|---|
USB Cable for JTAG/UART | Check Carrier Board and Programmer for correct typ |
XMOD Programmer | Carrier Board dependent, only if carrier has no own FTDI |
Content
For general structure and of the reference design, see Project Delivery
Design Sources
Type | Location | Notes |
---|---|---|
Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib <design name>/firmware | Vivado Project will be generated by TE Scripts |
SDK/HSI | <design name>/sw_lib | Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI |
PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
Additional Sources
Type | Location | Notes |
---|---|---|
SI5338 Project | \misc\SI5338 |
Prebuilt
File | File-Extension | Description |
---|---|---|
BIT-File | *.bit | FPGA (PL Part) Configuration File |
DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
Diverse Reports | --- | Report files in different formats |
Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI and PetaLinux |
LabTools Project-File | *.lpr | Vivado Labtools Project File |
MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) |
OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:
Design Flow
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:Vivado/SDK/SDSoC
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter for minimum setup
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
- Create HDF and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
- Create Linux (uboot.elf and image.ub) with exported HDF
- HDF is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
Important Note: Select correct Flash partition offset on petalinux-config: Subsystem Auto HW Settings → Flash Settings, FPGA+Boot+bootenv=0x900000 (increase automatically generate Boot partition), increas image size to A:, see Config
- Use TE Template from /os/petalinux
- HDF is exported to "prebuilt\hardware\<short name>"
- Add Linux files (uboot.elf and image.ub) to prebuilt folder
- "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
- "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
- (not longer needed manually: This will be done with Step 10.a automatically with newer scripts (2017.4.10) ) Generate UBoot SREC:
- Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_sdk
- Create "uboot-dummy" application
Note: Use Hello World Example - Copy u-boot.elf into "\workspace\sdk\uboot-dummy\Debug"
- Open "uboot-dummy" properties → C/C++ Build → Settings and go into Build Steps Tap.
- Add to Post-build steps: mb-objcopy -O srec u-boot.elf u-boot.srec
- Press Apply or regenerate project
Note: SREC is generated on "\workspace\sdk\uboot-dummy\Debug\u-boot.srec"
- Generate MCS Firmware (optional):
- Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_sdk
- Create "SCU" application
Note: Select MCS Microblaze and SCU Application - Select Release Built
- Regenerate App
- Generate Programming Files with HSI/SDK
- Run on Vivado TCL: TE::sw_run_hsi
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
Note: See SDK Projects
- Run on Vivado TCL: TE::sw_run_hsi
- Copy "\prebuilt\software\<short name>\srec_spi_bootloader.elf" into "\firmware\microblaze_0\"
- (optional) Copy "\\workspace\sdk\scu\Release\scu.elf" into "\firmware\microblaze_mcs_0\"
- Regenerate Vivado Project or Update Bitfile only with "srec_spi_bootloader.elf" and "scu.elf"
Launch
Programming
Check Module and Carrier TRMs for proper HW configuration before you try any design.
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
QSPI
- Connect JTAG and power on PCB
- (if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
- Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
Note: Alternative use SDK or setup Flash on Vivado manually
optional "TE::pr_program_flash_binfile -swapp hello_te0712" possible - Reboot (if not done automatically)
SD
Not used on this Example.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- Power on PCB
Note: FPGA Loads Bitfile from Flash,MCS Firmware configure SI5338 and starts Microblaze, SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), U-boot loads Linux from QSPI Flash into DDR
Boot process takes a while, please wait.
Linux
Note: Linux boot process is slower on Microblaze.
- Open Serial Console (e.g. putty)
- Speed: 9600
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:- User Name: root
- Password: root
- You can use Linux shell now.
- ETH0 works with udhcpc
- ETH0 works with udhcpc
Vivado HW Manager:
- Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
- Set radix from VIO signals (MGT REF, MIG_OUT, CLK1B, CLK0) to unsigned integer.
Note: Frequency Counter is inaccurate and displayed unit is Hz - MGT REF~125MHz, MIG_50MHZ~50MHz., CLK1B ~50MHz, CLK0~100MHz
- Additional Infos: System reset from MCS and GIO outputs
- Set radix from VIO signals (MGT REF, MIG_OUT, CLK1B, CLK0) to unsigned integer.
System Design - Vivado
Block Design
REV02
REV01
Same as REV02 but 50 MHz ETH REV CLK is generated from MIG output with 180° Phase shift.
Constrains
Basic module constrains
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property CONFIG_MODE SPIx4 [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design]
Design specific constrain
set_property PULLDOWN true [get_ports reset]
#I2C #set_property PACKAGE_PIN W21 [get_ports PLL_I2C_scl_io] #set_property IOSTANDARD LVCMOS33 [get_ports PLL_I2C_scl_io] #set_property PACKAGE_PIN T20 [get_ports PLL_I2C_sda_io] #set_property IOSTANDARD LVCMOS33 [get_ports PLL_I2C_sda_io] set_property PACKAGE_PIN W21 [get_ports PLL_I2C_ext_scl_o] set_property IOSTANDARD LVCMOS33 [get_ports PLL_I2C_ext_scl_o] set_property PACKAGE_PIN T20 [get_ports PLL_I2C_ext_sda] set_property IOSTANDARD LVCMOS33 [get_ports PLL_I2C_ext_sda] #Reset set_property PACKAGE_PIN T3 [get_ports reset] set_property IOSTANDARD LVCMOS15 [get_ports reset] #CLKS set_property PACKAGE_PIN R4 [get_ports {CLK1B[0]}] set_property IOSTANDARD LVCMOS15 [get_ports {CLK1B[0]}] set_property PACKAGE_PIN K4 [get_ports {CLK0_clk_p[0]}] set_property IOSTANDARD DIFF_SSTL15 [get_ports {CLK0_clk_p[0]}] #ETH PHY set_property PACKAGE_PIN N17 [get_ports phy_rst_n] set_property IOSTANDARD LVCMOS33 [get_ports phy_rst_n
create_clock -period 8.000 -name mgt_clk0_clk_p -waveform {0.000 4.000} [get_ports mgt_clk0_clk_p] create_clock -period 10.000 -name {CLK0_clk_p[0]} -waveform {0.000 5.000} [get_ports {CLK0_clk_p[0]}] create_clock -period 20.000 -name {CLK1B[0]} -waveform {0.000 10.000} [get_ports {CLK1B[0]}] create_clock -period 15.152 -name CFGMCLK -waveform {0.000 7.576} [get_pins -hierarchical -filter {NAME =~*NO_DUAL_QUAD_MODE.QSPI_NORMAL/*STARTUP_7SERIES_GEN.STARTUP2_7SERIES_inst/CFGMCLK}] set_false_path -from [get_clocks {CLK0_clk_p[0]}] -to [get_clocks clk_pll_i] set_false_path -from [get_clocks mgt_clk0_clk_p] -to [get_clocks clk_pll_i] set_false_path -from [get_pins {msys_i/SC0712_0/U0/rst_delay_i_reg[3]/C}] -to [get_pins -hierarchical -filter {NAME =~*u_msys_mig_7series_0_0_mig/u_ddr3_infrastructure/rstdiv0*/PRE}] set_false_path -from [get_clocks -of_objects [get_pins msys_i/mig_7series_0/u_msys_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT]] -to [get_clocks mgt_clk0_clk_p] set_false_path -from [get_clocks clk_pll_i] -to [get_clocks {msys_i/util_ds_buf_0/U0/IBUF_OUT[0]}] set_false_path -from [get_pins {msys_i/labtools_fmeter_0/U0/F_reg[*]/C}] -to [get_pins {msys_i/vio_0/inst/PROBE_IN_INST/probe_in_reg_reg[*]/D}] set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/COUNTER_REFCLK_inst/bl.DSP48E_2/CLK] -to [get_pins {msys_i/vio_0/inst/PROBE_IN_INST/probe_in_reg_reg[*]/D}] set_false_path -from [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CLK}] -to [get_pins {msys_i/labtools_fmeter_0/U0/F_reg[*]/D}]
Software Design - SDK/HSI
For SDK project creation, follow instructions from:
Application
Template location: ./sw_lib/sw_apps/
scu
MCS Firmware to configure SI5338 and Reset System.
srec_spi_bootloader
Boadloader to load app or second bootloader from flash into DDR
Changes:
- Add some vonsole outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash
xilisf_v5_11
- Changed default Flash Typ to 5.
hello_te0712
Hello TE0712 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate u-boot.srec. Vivado to generate *.mcs
Software Design - PetaLinux
Description currently not available.
Config
- Set kernel flash Address to 0x900000 and Kernel size to 0xA00000:
(--> Subsystem Auto Hardware Settings --> Flash Settings)- SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART0_SIZE = 0x5E0000
- SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART1_SIZE = 0x300000
- SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART2_SIZE = 0x20000
- SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART3_SIZE = 0xA00000
U-Boot
#include <configs/platform-auto.h> #define CONFIG_SYS_BOOTM_LEN 0xF000000 /* ethernet - axi_ethernetlite_0 */ #undef CONFIG_PHY_XILINX #undef XILINX_EMACLITE_BASEADDR 0x40E00000 #undef CONFIG_MII #undef CONFIG_NET_MULTI #undef CONFIG_NETCONSOLE 1 #undef CONFIG_SERVERIP 192.168.150.127 #undef CONFIG_IPADDR /* PREBOOT */ #define CONFIG_PREBOOT "echo U-BOOT for petalinux;setenv preboot; echo;"
Device Tree
/include/ "system-conf.dtsi" / { }; /* QSPI PHY */ &axi_quad_spi_0 { #address-cells = <1>; #size-cells = <0>; flash0: flash@0 { compatible = "jedec,spi-nor"; spi-tx-bus-width=<1>; spi-rx-bus-width=<4>; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <25000000>; }; }; /* ETH PHY */ &axi_ethernetlite_0 { phy-handle = <&phy0>; mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@0 { device_type = "ethernet-phy"; reg = <1>; }; }; };
Kernel
No changes.
Rootfs
No changes.
Applications
No changes.
Additional Software
SI5338
Download ClockBuilder Desktop for SI5338
- Install and start ClockBuilder
- Select SI5338
- Options → Open register map file
Note: File location <design name>/misc/Si5338/RegisterMap.txt - Modify settings
- Options → save C code header files
- Replace Header files from FSBL template with generated file
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
Date | Document Revision | Authors | Description |
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| |||
v.28 | John Hartfiel |
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v.27 | John Hartfiel |
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v.23 | John Hartfiel |
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v.22 | John Hartfiel |
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2018-02-13 | v.19 | John Hartfiel |
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2018-01-08 | v.16 | John Hartfiel |
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2017-12-15 | v.15 | John Hartfiel |
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2017-11-07 | v.11 | John Hartfiel |
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2017-10-06 | v.10 | John Hartfiel |
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2017-10-05 | v.8 | John Hartfiel |
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2017-09-11 | v.1 |
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All |
Legal Notices
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Document Warranty
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