The TE0630 module series has been designed to be compatible with the TE0300 module seriss by main mechanical and electrical characteristics.
TE0300 and TE0630 have similar power requirements and matched power input pins. User signals to B2B connectors routed as differential pairs and single ended lines. Differences in pin types shown in Table 16, not listed signals have same or compatibleSignals routed as differential pairs can be used as single ended. type.
Connector:Pin | TE0300 | TE0300 type | TE0630 pin name | TE0630 type |
---|---|---|---|---|
J4:5 | B3_L01_P | DIO | V3_IO_01 | SIO |
J4:7 | B3_L01_N | DIO | V3_IO_02 | SIO |
J4:9 | B3_L02_P | DIO | V3_IO_03 | SIO |
J4:11 | B3_L02_N | DIO | V3_IO_04 | SIO |
J4:17 | B0_L24_N | DIO | V0_IO_01 | SIO |
J4:19 | B0_L24_P | DIO | V0_IO_01_N | DIO |
J4:6 | B3_L07_P | DIO | V3_IO_06 | SIO |
J4:8 | B3_L07_N | DIO | V3_IO_07 | SIO |
J4:10 | B3_L03_N | DIO | V3_IO_08 | SIO |
J4:12 | B3_L03_P | DIO | V3_IO_09 | SIO |
J5:13 | B3_L22_P | DIO | V3_IO_12 | SIO |
J5:15 | B3_L22_N | DIO | V3_IO_13 | SIO |
J5:19 | B3_L20_P | DIO | V3_IO_14 | SIO |
J5:21 | B3_L20_N | DIO | V3_IO_15 | SIO |
J5:16 | B3_L21_N | DIO | V3_IO_17 | SIO |
J5:18 | B3_L21_P | DIO | V3_IO_18 | SIO |
J5:20 | B3_L23_N | DIO | V3_IO_19 | SIO |
J5:22 | B3_L23_P | DIO | V3_IO_20 | SIO |
J5:32 | B2_L06_P | DIO | V3_IO_24 | SIO |
J5:34 | B2_L06_N | DIO | V3_IO_25 | SIO |
J5:41 | B2_GCLK13 | CIO | V2_IO_02 | SIO |
J5:49 | B2_GCLK_L13_N | CIO | V2_IO_24_P | DIO |
J5:51 | B2_GCLK_L13_P | CIO | V2_IO_24_N | DIO |
Table 16: TE0300 and TE0630 pin types differences.
See Table 17 for pin types definitions.
Type | Description |
---|---|
DIO | Unrestricted, general-purpose differential user-I/O pin. |
SIO | Unrestricted, general-purpose user-I/O pin. |
CIO | Unrestricted, general-purpose differential user-I/O pin. This pin also can be used as FPGA clock input. |
Table 17: TE0300 and TE0630 pin types
Most user signals to B2B connectors routed from same FPGA banks. Differences shown in Table 18.
Connector:Pin | TE0300 Bank | TE0630 Bank |
---|---|---|
J4:15 | 0 | 3 |
J4:36 | 0 | 3 |
J4:52 | 0 | 3 |
J5:33 | 2 | 3 |
J5:28 | 2 | 3 |
J5:30 | 2 | 3 |
J5:32 | 2 | 3 |
J5:34 | 2 | 3 |
J5:38 | 2 | 3 |
J5:40 | 3 | 2 |
J5:42 | 3 | 2 |
J5:50 | 3 | 2 |
J5:52 | 3 | 2 |
Table 18: TE0300 and TE0630 user signals I/O banks differences.
I/O Banks power supply for both modules shown in Table 19.
Bank | TE0300 | TE0630 |
---|---|---|
B0 | VCCIO (1.2 V - 3.3 V) | VCCIO (1.2 V - 3.3 V) |
B1 | 2.5 V | 1.5 V |
B2 | 3.3 V | 3.3 V |
B3 | 3.3 V | 3.3 V |
Table 19: TE0300 and TE0630 FPGA I/O banks power supply.
Bank 0 I/O supply voltage at both modules can be configured by user, see chapter On-board Power Rails.
The TE0630 is mechanically equivalent to the TE0300: