Recommended Design Tools Settings

When the configuration process successfully completes, the FPGA either actively drives the DONE pin High (DriveDone) or allows the DONE pin to float High using either an internal or external pull-up resistor, controlled by the DonePin bitstream generator option. To have DONE LED D1 lit after successful FPGA configuration, DriveDone and DonePin bitstream generator options for the DONE pin have to be set to have DONE actively driving its line (see Figure 56 and Table 32).
Figure 56: DriveDone and DonePin set to have DONE actively driving its line.
DriveDone defines whether the DONE pin is an active driver or an open-drain output.
DonePin defines whether or not the DONE pin has an internal pull-up resistor.

Table 32: DriveDone and DonePin settings for having DONE actively driving its line.
See Xilinx UG332: Spartan-3 Generation Configuration User Guide (paragraph "DONE Pin") for additional information on these signals.
This options are set graphically in Xilinx ISE Software Project Navigator by selecting the following:
Generate Programming File > Process Properties > Startup Options > Drive Done Pin High > check the box
Generate Programming File > Process Properties > Configuration Options > Configuration Pin Done > float

Table 33: Xilinx ISE Project Navigator settings for having DONE actively driving its line.
Consult ISE Help about the Process Properties of the Generate Programming File process in the Processes pane for additional information on these properties.

All signals entering and exiting a Xilinx Spartan-3 generation FPGA must pass through the I/O resources, known as I/O blocks or IOBs. Users can specify the configuration for any unused IOB pins. This is the serial data outputs for all JTAG instruction and data registers.
This options are set graphically in Xilinx ISE Software Project Navigator by selecting the following:
Generate Programming File > Process Properties > Configuration Options > Unused IOB Pins
Select an option from the drop-down list.

1. Pull DownDefault. All unused I/O pins and input-only pins have a pull-down resistor to GND.
2. Pull UpAll unused I/O pins and input-only pins have a pull-up resistor to the VCCO_# supply for its associated I/O bank.
3. Float (also: Pullnone)All unused I/O pins and input-only pins are left floating (Hi-Z, high-impedance, three-state). Use external pull-up or pulldown resistors or logic to apply a valid signal level.