Configuration of USB (firmware, EEPROM) and FPGA (bitstream, SPI Flash)

IIC EEPROM and USB FX2 microcontroller Configuration

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FPGA Configuration

The Xilinx Spartan-3E FPGA on the TE0300, Xilinx Spartan-3A DSP FPGA on the TE0320, Xilinx Spartan-6 FPGA on the TE0630 can be configured in the following ways:

• B2B connector
  • JTAG
  • Slave Parallel (SelectMAP)
  • Slave Parallel
• 6-pin JTAG header connector
• SPI Flash memory (see the next section)

For further information on

• Xilinx Spartan-3E FPGA
• Xilinx Spartan-3A DSP configuration modes, please consult the documentation listed in chapter 17 Related Materials and References.
• Xilinx Spartan-6

SPI Flash Configuration ( if the module exit from reset or is powered on, the SPI flash content program/configure the FPGA)

The bit-stream for the FPGA is stored in the SPI Flash. To use this bit-stream source FPGA configuration option is set to “Master Serial/SPI”. See 2.8 SPI Flash for additional information.

SPI Flash can be programmed in several ways:

• Direct programming by USB controller (usually done by Firmware Upgrade Tools like Python OpenFut and C# OpenFutNet).

• Indirect SPI programming via FPGA pins, controlled by JTAG (can be done using Xilinx iMPACT). See Appendix A. Indirect SPI Programming using iMPACT.

• Direct SPI programming by FPGA, using an SPI core (FPGA project should contain SPI interface core and software to work with it: only if iMPACT GUI is version 11.x or below, see Xilinx AR#36156)).