FPGA User I_Os

A total of 110 FPGA user I/Os are available on corresponding contacts of B2B connectors J4 and J5 (see Appendix).
37 differential digital I/O pairs:each pair is configurable as 2 single-ended digital I/Os, corresponding to a maximum of 74 single-ended digital I/Os;
4 differential clock input pairs:each pair is configurable as differential digital I/O pair or 2 single-ended clock inputs or 2 single-ended digital I/Os (or combination thereof), corresponding to from a maximum of 8 independent clock inputs to a maximum of 8 independent digital I/Os;
1 differential clock input pair:the pair is configurable as differential digital input pair or as 2 single-ended clock inputs or 2 single-ended digital inputs (or combination thereof), corresponding to from a maximum of 2 independent clock inputs to a maximum of 2 independent digital inputs;
21 single-ended digital I/Os;
5 single-ended inputs.
Table 4 summarizes the maximum available FPGA user I/Os divided by supply voltage.

Table 4: maximum FPGA user I/Os by supply voltage.