TE USB FX2 module is equipped with a Cypress EZ-USB FX2 controller to provide a high-speed USB 2.0 interface. The controller uses 4 interfaces (see here):
- USB interface (to USB connector);
- I2C interface (to EEPROM);
- SPI interface (to FPGA and Flash);
- FIFO interface (to FPGA).
The I2C interface connects the USB controller to the EEPROM chip, which stores vendor ID and device ID. See chapter DIP Switch for available options.
The SPI interface id used to communicate with the FPGA and to access the SPI serial Flash chip.
The FIFO interface provides a high-speed communication channel with the FPGA. The interface can transfer up to 48 MB/s burst rate.
To program the firmware in the EEPROM, the IIC bus should be correctly configured.
To program the bitstream in the Flash, the SPI bus should be correctly configured.
TE USB FX2 modules can be configured through a host computer with the following system requirements:
- Operating system: Microsoft Windows 2000, Microsoft Windows XP, Microsoft Vista or above;
- Xilinx ISE 10.1 or later for indirect SPI in-system programming (ISP) (for Spartan-3E aka TE0300, see Xilinx Answer AR #25377);
- Xilinx EDK for some reference designs;
- Interface: USB host;
- JTAG cable with flying leads.
- SPI USB cable with flying leads (for TE0300): direct SPI in-system programming (ISP) is only possible until iMPACT 11.x.
Overview
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