Xilinx 7 Series FPGA
Zynq-7000
Xilinx AR5774 deals with the problem and provides some workarounds.
| # | Good | Bad | |
|---|---|---|---|
| 1 | Limit the access to lower 16Mbytes | No change of code or hardware | Only 16MBytes can be accessed safely, may have to take special actions to actually limit the access to lower 16Mbyte |
| 2 | Preload from upper 16Mbytes in FSBL, limit access to 16Mbytes after FSBL handout | Only FSBL changes needed | Access above 16MByte should not be performed from SSBL or application code. |
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