SPI 32 Bit Addressing

Xilinx 7 Series FPGA

Xilinx AR5774 deals with the problem and provides some workarounds.

#		Good	Bad
1	Limit the access to lower 16Mbytes	No change of code or hardware	Only 16MBytes can be accessed safely, may have to take special actions to actually limit the access to lower 16Mbyte
2	Preload everything above 16Mbytes in FSBL, limit access to lower 16Mbytes after FSBL handout	Only FSBL changes needed	Access above 16MByte should not be performed from SSBL or application code.
3	Rewrite FSBL, SSBL and OS/RTOS Drivers to avoid using EAR register and "legacy mode"	Truly safe solution, no hardware changes no restriction on SPI Flash Partitioning. Very good solution for bare metal applications.	A lot of Code and drivers to modify, the patches have to be applied again after each software release. Access to SPI Flash above 16Mbyte must be done using SPIx1 mode command set.
4	Place "reboot.bin" at 16MByte boundary	No change of code of hardware.	256KByte sector at 16Mbyte offset in SPI Flash is "reserved" it must contain the "reboot.bin" image. If reset occurs while EAR=! 0 then Zynq PS is doing double reset sequence, first the reboot.bin executes, then it clears EAR and forces reboot that then starts normally from Flash Address 0. However reboot.bin does not perform any peripheral or memory or PLL init and executes very fast so the extra delay in startup is small.