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Overview


CPLD Device with designator U46: 10M08SAU169

Feature Summary

  • something to have access to CPLD to read out status of Power management
  • Power management
  • Reset

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification


Port Description

Name / opt. VHD NameDirectionPinPullup/DownBank Power

Description

JTAGEN
inE5--3.3Vfixed to 3.3V
TCK_MAX10inG2--3.3VJTAG 
TMS_MAX10inG1--3.3VJTAG
TDO_MAX10outF6--3.3VJTAG 
TDI_MAX10inF5--3.3VJTAG 
 


 
EN_VTT_PL_DDRoutJ2
3.3V LVCMOS
  • Enable signal for TPS51206 (U26)
  • VTT: VTT_DDR_PL
  • VTTREF: VREFA_DDR_PL
EN_2V5_PL_DDRoutJ1
3.3V LVCMOS
  • Enable signal for TPS82130 (U22)
  • VOUT: +2.5V_PL_DDR
  • PG: PG_+2.5V_PL_DR
EN_1V2_PL_DDRoutH4
3.3V LVCMOS
  • Enable signal for TPS82130 (U24)
  • VOUT: +1.2V_PL_DDR
  • PG: PG_+1.2V_PL_DR
PG_1V2_PL_DDRinH5weak pull-up3.3V LVCMOS
  • PowerGood output signal from TPS82130 (U24)
EN_1V8_PS_AUXoutM2
3.3V LVCMOS
  • Enable signal for TPS72018 (U43)
  • VOUT: +1.8V_AUX_PS
PG_SOMoutM1weak pull-up3.3V LVCMOS
  • PowerGood output signal connected to J2B (D51)
  • in TEBT0865:
    • enable signal for TPS82130 (U2) → Carrier_+1.8V
    • PWRGD signal for TPS54240 (U14) → Carrier_+1.8V
PG_VCCINTinN3weak pull-up3.3V LVCMOS
  • PowerGood output signal from LTM4700 (U20)
LTM_FAULTinN2
3.3V LVCMOS
  • FAULT signal from LTM4700 (U20)
SC_EXT_2outL3
3.3V LVCMOS
  • SC_EXT2 output signal connected to J2B (D52)
  • in TEBT0865:
    • enable signal for USB TPS82130 (U12)
  • Deactivated on delivery
M_SDAinoutM3
3.3V LVCMOS
  • connected to level shifter TXS0102 (U12)
  • connected to EEPROM 24AA025 (U14)
  • connected to SLS32AIA (U16)
  • connected to ATECC608B-MAH (U19)
MRoutK2
3.3V LVCMOS
  • Manual Reset 
  • actual configured as output and set to 1.
  • Should be an input for monitoring???
EN_SOMinK1weak pull-up3.3V LVCMOS
  • SC_EXT4 input signal connected to J2B (D54)
  • in TEBT0865:
    • PG signal from TPS82130 (U3)→ Carrier_+1.8V
    • PWRGD signal for TPS54240 (U15)→ Carrier_+1.8V
SC_EXT_3inL2
3.3V LVCMOS
  • SC_EXT3 input signal connected to J2B (D53)
  • in TEBT0865:
    • Overcurrent Signal from TPS2051 (U9)






SMB_ALERTnin L4
3.3V LVCMOS
  • Alert signal from LTM4700 (U20)
PG_2V5_PL_DDRin L5weak pull-up3.3V LVCMOS
  • PowerGood output signal from TPS82130 (U22)
EN_LTM_RUNPout
M5
3.3V LVCMOS
  • RUNP signal from LTM4700 (U20)
    • enables board bias circuit to supply IC and to drive the MOSFET when the SVin is higher than 7V.
    • Needs to be '1' ; Tie to ground to disable the bias circuit when Vin is less than 5,75V
M_SCL inoutM4
3.3V LVCMOS
  • connected to level shifter TXS0102 (U12)
  • connected to EEPROM 24AA025 (U14)
  • connected to SLS32AIA (U16)
  • connected to ATECC608B-MAH (U19)
nRST_SYS outK5
3.3V LVCMOS
  • System reset output signal, resets eMMC, ETH-Phy and USB-Phy
EN_0V9_GTH_AVCCout
N5
3.3V LVCMOS
  • Enable signal for TPS82130 (U35)
EN_0V9_GTY_AVCCout
N4
3.3V LVCMOS
  • Enable signal for TPS82130 (U38)

PG_1V2_PS_DDR

in 
M7weak pull-up3.3V LVCMOS
  • PowerGood output signal from TPS82130 (U25)

PG_0V9_GTH_AVCC

 inN6weak pull-up3.3V LVCMOS
  • PowerGood output signal from LT8642 (U35)

PG_0V9_GTY_AVCC

 inN8weak pull-up3.3V LVCMOS
  • PowerGood output signal from LT8642 (U38)
EN_3V3_SWout
N7
3.3V LVCMOS
  • enable signal for SIP32408 (U52)
EN_1V2_PS_PLLout
J6
3.3V LVCMOS
  • Enable signal for TPS72012 (U42)

PG_1V8_PS_GTR_AVTT

 inM9weak pull-up3.3V LVCMOS
  • PowerGood output signal from TPS82130 (U47)

PG_1V8

 inM8weak pull-up3.3V LVCMOS
  • PowerGood output signal from TPS82130 (U41)
EN_2V5_PS_DDRout
M13
3.3V LVCMOS
  • Enable signal for TPS82130 (U23)
PG_1V2_GTY_AVTT inN9weak pull-up3.3V LVCMOS
  • PowerGood output signal from LT8642 (U39)
EN_1V2_GTY_AVTTout
N10
3.3V LVCMOS
  • Enable signal for LT8642 (U39)
M_INT L11
3.3V LVCMOS
EN_1V8_VCC_ADCout
M11
3.3V LVCMOS
  • Enable signal for TPS72018 (U49)
  • VOUT: +1.8V_VCCADC
PG_0V85_PS_GTR_AVCC inK8weak pull-up3.3V LVCMOS
  • PowerGood output signal from TPS74801 (U48)
EN_VTT_PS_DDRout
J8
3.3V LVCMOS
  • Enable signal for TPS51206 (U27)
  • VTT: VTT_DDR_PS
  • VTTREF: VREFA_DDR_PS
EN_1V8out
L10
3.3V LVCMOS
  • Enable signal for TPS82130 (U41)
EN_1V8_GTY_AUXout
M10
3.3V LVCMOS
  • Enable signal for TPS72018 (U40)
  • VOUT: +1.8V_GTY_AUX
PG_2V3 inN12weak pull-up3.3V LVCMOS
  • PowerGood output signal from TPS82130 (U45)

 






EN_1V8_GTR_AVTT_PS

out
 K10
3.3V LVCMOS
  • enable signal for TPS82130 (U47)

EN_1V8_GTH_AUX

out
 K11
3.3V LVCMOS
  • enable signal for TPS72018 (U37)
  • VOUT: +1.8V_GTH_AUX

EN_1V8_AUX

out
K12
3.3V LVCMOS
  • enable signal for TPS82130 (U50)

EN_1V2_GTH_AVTT

out
J12
3.3V LVCMOS
  • enable signal for LT8642 (U36)

PG_3V3_SW

inJ9weak pull-up3.3V LVCMOS
  • output voltage from secondary power SIP32408 (U52)

EN_1V2_PS_DDR

out
J13
3.3V LVCMOS
  • enable signal for TPS82130 (U25)

EN_0V85_GTR_AVCC_PS

out
H13
3.3V LVCMOS
  • enable signal for TPS74801 (U48)

PG_1V2_GTH_AVTT

inH9weak pull-up3.3V LVCMOS
  • PowerGood output signal from LT8642 (U36)

EN_VCCINT

out
H8
3.3V LVCMOS
  • enable signal for LTM4700 (U20)

EN_2V3

out
G13
3.3V LVCMOS
  • enable signal for TPS82130 (U45)

PG_1V8_AUX

inG12weak pull-up3.3V LVCMOS
  • PowerGood output signal from TPS82130 (U50)

PG_2V5_PS_DDR

inL13weak pull-up3.3V LVCMOS
  • PowerGood output signal from TPS82130 (U23)

Functional Description


Power

All power regulators are controlled by the power sequencer core. It enables and discharges the power regulators and monitors the power good signals.

The power-up sequence corresponds to AMD's recommendations and is shown in the table below:

Power Group

Power enable signal

(CPLD output signal)

Power good signal

(CPLD input signal)

Notes

0

--

EN_SOM

 



1


EN_VCCINT

PG_VCCINT

--

EN_2V3

PG_2V3

--

EN_3V3_SW

PG_3V3_SW

+3.3V_SW output signal from U52





2






EN_1V8

PG_1V8

--

EN_1V8_AUX

PG_1V8_AUX

--

EN_1V8_PS_AUX

--

--

EN_1V2_PS_PLL

--

--

EN_0V9_GTH_AVCC

PG_0V9_GTH_AVCC

--

EN_0V9_GTY_AVCC

PG_0V9_GTY_AVCC

--

EN_1V8_VCC_ADC

--

--



3




EN_1V2_PS_DDRPG_1V2_PS_DDR--
EN_1V2_PL_DDRPG_1V2_PL_DDR--
EN_1V2_GTH_AVTTPG_1V2_GTH_AVTT--
EN_1V2_GTY_AVTTPG_1V2_GTY_AVTT--





4

 

EN_VTT_PS_DDR

--

--

EN_0V85_PS_GTR_AVCC

PG_0V85_PS_GTR_AVCC

--

EN_VTT_PL_DDR

--

--

EN_2V5_PL_DDR

PG_2V5_PL_DDR

--

EN_2V5_PS_DDR

PG_2V5_PS_DDR

--

EN_1V8_GTH_AUX

--

--

EN_1V8_GTY_AUX

--

--

5

EN_1V8_PS_GTR_AVTT

PG_1V8_PS_GTR_AVTT

--

6

PG_SOM

--

--


JTAG UART

As the power sequencer monitors all voltages and there is no visual feedback in the event of an error, the JTAG UART was implemented.

The command "nios2-terminal.exe" in the NIOS II command shell is used to output the power good signals and the revision of the CPLD firmware and the PCB.


see also https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/jtag-uart-core.html



I2C interface

CPLD firmware consists of an I2C Slave to Avalon-MM Master Bridge Intel FPGA IP i2c t GPIO block. This subsystem provides i2c protocol interface to  32-bit (4 x 8-bit) (GPIO_input[31:0]) registers for reading from CPLD and (4 x 8-bit) (GPIO_output[31:0]) registers for writing in CPLD as general purpose parallel input and output (I/Os). The written and read data is communicated from/to FPGA via i2c bus interface protocol. The address of this block in the firmware is 0x20. In this case related i2c bus is bus 1. 



RegisterDirection in CPLDAddress
GPIO_input[7:0]Output (reading from CPLD)0x00
GPIO_input[15:8]Output (reading from CPLD)0x01
GPIO_input[23:16]Output (reading from CPLD)0x02
GPIO_input[31:24]Output (reading from CPLD)0x03
GPIO_output[7:0]Input (writing to CPLD)0x00
GPIO_output[15:8]Input (writing to CPLD)0x01
GPIO_output[23:16]Input (writing to CPLD)0x02
GPIO_output[31:24]Input (writing to CPLD)0x03

NOSEQ pin

This pin in PCB REV04 with old CPLD firmware version (REV04) is  used as boot mode pin select. If  CPLD is programmed with SC0820_qspi_sd_jtag.jed as jed file and  NOSEQ is  high, JTAG boot mode will be selected. For PCB REV05 or PCB REV04 with new CPLD firmware (CPLD firmware REV05) NOSEQ pin can be used by user as GPIO pin and accessed via i2c interface. In this case the following table can be used:

NOSEQ pin as outputConditionCommand in linux console
'1'GPIO_output(16) = '1'
i2cset -y 1 0x20 0x02 0x01
'0'GPIO_output(16) = '0'
i2cset -y 1 0x20 0x02 0x00
NOSEQ pin as inputDescriptionCommand in linux console
Reading state of NOSEQ pinGPIO_input(16) = NOSEQ
i2cget -y 1 0x20 0x02


Access to CPLD Registers

CPLD registers can be accessed via i2c interface. In the following table is shown how these registers can be read or written:

Register AddressDirection in CPLDRelated instruction in linux console to access the register
0x00Output (reading from CPLD)i2cget -y 1 0x20 0x00
0x01Output (reading from CPLD)i2cget -y 1 0x20 0x01
0x0CInput (writing to CPLD)i2cset -y 1 0x20 0x00 <data>
GPIO_output[15:8]Input (writing to CPLD)i2cset -y 1 0x20 0x01 <data>
GPIO_output[23:16]Input (writing to CPLD)i2cset -y 1 0x20 0x02 <data>
GPIO_output[31:24]Input (writing to CPLD)

i2cset -y 1 0x20 0x03 <data>

Some of these registers are using to show some information same as  CPLD revision and boot mode while booting.

RegisterAddressrelated  dataRead/write by userDescription
GPIO_input[7:0]0x00CPLD REVISION (8 bits)No
GPIO_input[15:8]0x01"00" & BOOTMODE_GEN (2 bits) &  PUDC (1 bit) & CPLD_BM (1 bit) & BOOT_MODE (2 bits)No

BOOTMODE_GEN is a generic parameter in firmware code to select type of jed-file. For example if this parameter is 3 , then by programming the related jed-file the user can have all boot mode options. (QSPI/JTAG/SD Card/eMMC).

PUDC is the state of PUDC pin of FPGA.

CPLD_BM is a parameter to show if boot mode selection is executed via hardware ( if low) or software (if high)

BOOT_MODE shows selected boot mode.

GPIO_input8[16]0x02NOSEQ pinYes
RegisterAddressrelated data
Description
GPIO_output[16]0x02NOSEQ pinYes

If CPLD firmware version is  REV05, then boot mode, CPLD revision and some features of the board will be displayed in the linux console via FSBL code  while booting. The format of these informations are shown in the following:

InformationDisplayed in Linux consoleDescription
CPLD RevisionCPLD_REV = <cpld revision>
Boot mode selection procedureCPLD_BM = < bm selection procedure>
  • If boot mode via hardware is selected → Deactive(0)
  • If boot mode via software (in linux console or via FSBL code) is selected → Active(1)
Jed file that on CPLD is programmedBOOTMODE_GEN = < jed file type>
  • Jed file type can be one of the following types :
    • (0) QSPI/SD
    • (1) QSPI/JTAG
    • (2) JTAG/SD
    • (3) default QSPI/JTAG/SD/eMMC
PUDC pin statePUDC_MODE = <pudc state>
  • PUDC can have one of the following state:
    • Pull-up activated (0)
    • Pull-up deactivated (1)
Boot modeBOOT_MODE = <boot mode>
  • The following boot modes can displayed:
    • eMMC (0)
    • JTAG (1)
    • QSPI (2)
    • SD Card (3)

The CPLD revision, boot mode and other informations will be displayed while booting as shown:

All information while booting

If PCB revision is REV04 and  CPLD firmware version is older than REV05 (for example REV04) , then it will not be displayed these informations same as  boot mode while booting and the following message will be displayed:

Message while booting if CPLD firmware version is old for PCB REV04


Appx. A: Change History

For PCB REV01 and REV02 Documentation available on: TE0820-REV01_REV02 CPLD

Revision Changes

  • REV02 to REV03
    • changed top design from block design to text design
  • REV01 to REV02
    • added Pin L3 SC_EXT_2 as output and set to VCC to enable USB

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

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REV03REV02

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All

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Appx. B: Legal Notices

Data Privacy

Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

Limitation of Liability

In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.

Copyright Notice

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.

Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.


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