TE0710 TRM

Overview

Trenz Electronic TE0710 is an industrial-grade FPGA module integrating a Xilinx Artix-7 FPGA, Dual 10/100 MBit Ethernet PHYs, 512 MByte DDR3 SDRAM with 8-bit data-width, 32 MByte Quad SPI Flash memory for configuration and operation and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips. All modules in 4 x 5 cm form factor are mechanically compatible.

All this on a tiny footprint, smaller than a credit card, at the most competitive price.

Block Diagram

Figure 1: TE0710-02 Block Diagram

Main Components

Figure 2: TE0710 (REV 02).

1. Artix-7 (15T to 100T) FPGA
2. TPS51206 DDR3-SDRAM voltage supply
3. MEM4G08D3EABG 512 MByte DDR3 SDRAM
4. EN5311QI Voltage Regulator 1.5V
5.  S25FL256S 32 Mbyte Quad SPI Flash memory
6. System Controller CPLD (Lattice LCMXO2-256HC): 256 Macrocell CPLD
7. EN6347QI voltage Regulator 1.0V
8. SiT8008AI 25 MHz Ethernet reference clock
9. B2B connector JM2 (0,40 mm Razor Beam™ High Speed Hermaphroditic Terminal/Socket Strip (LSHM-150))
10. B2B connector JM1 (0,40 mm Razor Beam™ High Speed Hermaphroditic Terminal/Socket Strip (LSHM-150))
11. EN5311QI voltage Regulator 1.8V
12. TLK106 10/100 Mbps Ethernet PHY
13. TLK106 10/100 Mbps Ethernet PHY
14. 11AA02E48T-I/TT 2 Kbit EEPROM with UNI/O serial interface
    
15. SiT8008AI 100 MHz reference clock (connected to FPGA bank 35)

Key Features

• Industrial-grade Xilinx Artix-7 (15T to 100T) SoM (System on Module), supported by the free Xilinx Vivado WebPACK tool

• Rugged for shock and high vibration

• 512 MByte DDR3 SDRAM

• Dual 10/100 MBit Ethernet PHY

  • MAC Address EEPROM

• 32 MByte QSPI Flash memory (with XiP support)

• 100 MHz MEMS oscillator

• Plug-on module with 2 × 100-pin high-speed hermaphroditic strips

• 112 FPGA I/Os (51 differential pairs) are available on board-to-board connectors

• On-board high-efficiency DC-DC converters

  • 4.0 A x 1.0 V power rail

  • 1.0 A x 1.8 V power rail

  • 1.0 A x 1.5 V power rail

• System management and power sequencing

• eFUSE bit-stream encryption

• AES bit-stream encryption

• User LED

• Evenly-spread supply pins for good signal integrity

Assembly options for cost or performance optimization available upon request.

Initial Delivery State

Table 1: Initial delivery state

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

I/O signals connected to the FPGA's I/O banks and B2B connector:

 Table 2:  Voltage ranges and pin-outs of available logic banks of the FPGA

Please use Master Pinout Table table as primary reference for the pin mapping information.

JTAG Interface

JTAG access to the Xilinx Artix-7 and to the System Controller CPLD is provided through B2B connector JM2.

Table 3: Pin-mapping of JTAG Interface on B2B connector

System Controller I/O Pins

Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

Table 4: Pin-description of System Controller CPLD

LEDs

On the SoM TE0710 there is a total of 3 LEDS available. Two LEDs are status LEDs, one can freely used in costumer designs. The user LED is routed to the FPGA by the net with the schematic-name 'USERLED'.

When the FPGA is not configured the status LEDs will flash continuously. Finally once FPGA configuration has completed the status LEDs can be used in the user's FPGA design.

Table 5: Description of the on board LEDs

Clocking

The TE0710 is equipped with two Sitara reference clocks to provide clock signals to the Ethernet PHYs and for the on board 512 MByte DDR3 SRRAM.

Table 6: Clocks overview

Onboard Peripherals

32 Mbyte Quad SPI Flash Memory

An SPI flash memory S25FL256S (U7) is provided for FPGA configuration file storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data rate will be dependent on the bus width and clock frequency.

System Controller

The system controller is used to coordinate the configuration of the FPGA. The FPGA is held in reset (by driving the PROG_B signal) until the power supplies have sequenced. Low level at RESIN pin also resets the FPGA. This signal can be driven from the user’s PCB via the B2B connector pin JM2-18. Input EN1 is also gated to FPGA Reset, should be open or pulled up for normal operation. EN1 low does not turn off on board DCDC converters.

It is possible for the user to create their own system controller design using the Lattice Diamond software. Once created the design can be programmed into the device using the JTAG pins. The signal JTAGEN should be set to 3.3V to enable programming mode. For normal operation it should be set to 0V.

There are two LEDs that are connected to the system controller. When the FPGA is not configured the LEDs will flash continuously. Finally once FPGA configuration has completed the LEDs can be used in the user's FPGA design.

DDR3 SDRAM

Power and Power-On Sequence

Power Supply

Power supply with minimum current capability of 2A for system startup is recommended.

Table 7: maximal current of power supplies

Lowest power consumption is achieved when powering the module from single 3.3V supply. When using split 3.3V/5V supplies the power consumption (and heat dissipation) will rise, this is due to the DC/DC converter efficiency (it decreases when VIN/VOUT ratio rises).

Power-On Sequence

For highest efficiency of on board DC/DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

It is important that all baseboard I/O's are 3-stated at power-on until System Controller sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10,12 or 91, meaning that all on-module voltages have become stable and module is properly powered up.

See Xilinx datasheet DS181 (for Artix7) for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0710 module.

A 3.3V supply is also needed and must be supplied from the user's PCB. An output 3.3V supply is available on some of the board connector pins (see section 'Power Rails'). The input 3.3VIN will be switched to the internal 3.3V voltage level after the FPGA 1.0V supply is stable. Than 3.3V supply will be available on the B2B connector pins.

The regulators can be powered from the 3.3V supply or a 5V supply if preferred. The options for powering the board are as follows:

• Apply 5V to pins VIN and 3.3V to pins 3.3VIN on the board connector
• Apply 3.3V to pins VIN and 3.3VIN on the board connectors.

Power Rails

Table 8: Power rails of SoM on B2B connectors

Bank Voltages

Table 9: Range of FPGA's bank voltages

See the Artix7 datasheet DS181 for the allowable voltage range.

Board to Board Connectors

Variants Currently In Production

Table 10: Differences between variants of Module TE0710-02

Technical Specifications

Absolute Maximum Ratings

Table 11: Absolute maximum ratings

Recommended Operation Conditions

Table 12: Recommended operation conditions

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 50 mm × 40 mm.  Please download the assembly diagram for exact numbers.
• Mating height with standard connectors: 8mm
• PCB thickness: 1.6mm
• Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers.

All dimensions are shown in mm.

Figure 3: Physical Dimensions of the TE0710-02 board

Weight

Revision History

Hardware Revision History

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Document Change History

Date	Revision	Contributors	Description
2016-12-19		Ali Naseri	TRM revision
2015-01-23	0.1		initial version

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