Table of contents
CPLD Device with designator U5: LCMX02-1200HC. CC703S is minimum startup design.
- JTAG Management
- UART Management
- Power Management
- Boot Mode Management
- Reset Management
- LED Management
Firmware Revision and supported PCB Revision
See Document Change History
|Name / opt. VHD Name||Direction||Pin||Description|
|CM0||in||76||DIP-S2 / used as JTAG Selection|
|EN1||out||81||B2B Power Enable|
|FL_0||inout||28||LED (D3-red) / Status / not connected on REV02,REV03,REV04|
|FL_1||inout||27||LED (D4-green) / Status / not connected on REV02,REV03,REV04|
|FT_B_TX / BDBUS0||in||139||FTDI UART|
|JTAGEN||120||Enable JTAG access to CPLD for Firmware update (zero: normal IOs, one: CPLD JTAG access). Selectable over S2-3|
|M_TCK||in||131||JTAG from/to FTDI|
|M_TDI||in||136||JTAG from/to FTDI|
|M_TDO||out||137||JTAG from/to FTDI|
|M_TMS||in||130||JTAG from/to FTDI|
|MIO0||in||94||DIP-S4 and B2B Pin / used as Boot Mode|
|MIO12||in||100||B2B-Module UART2 TX|
|MIO13||out||99||B2B-Module UART2 RX|
|MIO14||out||105||B2B-Module UART RX|
|MIO15||in||95||B2B-Module UART TX|
|MIO9||out||96||SD_CD / not usable as SD_CD on REV02,REV03,REV04|
|MODE||out||83||Boot Mode Pin. Switch Boot mode of Module (depends on module)|
|NOSEQ||inout||78||Add Pullup only / currently_not_used|
|PGOOD||inout||82||Add Pullup used for Status / currently_not_used|
|PHY_LED1||out||86||Status / currently_not_used|
|PHY_LED1R||out||92||Status / currently_not_used|
|PHY_LED2||out||85||Status / currently_not_used|
|PHY_LED2R||out||91||Status / currently_not_used|
|PROGMODE||out||104||Enable B2B Module JTAG access to CPLD for Firmware update|
|RESIN||out||119||Module Reset Pin on B2B connector|
|S1||in||114||Push Button / Used as module Reset|
|SD_CD||in||93||Forward to MIO 9 / not connected on REV02,REV03,REV04|
|SD_SEL||out||113||set to GND / currently_not_used|
|TCK_B||out||1||JTAG from/to Module|
|TDI_B||out||3||JTAG from/to Module|
|TDO_B / C_TDO||in||2||JTAG from/to Module|
|TMS_B||out||4||JTAG from/to Module|
|ULED1 / LED1||out||117||LED (D1-red) / UART Monitoring|
|ULED2 / LED2||out||115||LED /D2-green) / UART Monitoring|
|X16||in||59||UART2 on VG connector J2|
|X17||out||60||UART2 on VG connector J2|
JTAG signals routed directly through the CPLD to module in B2B connector. Access between CPLD and module can be multiplexed via JTAGEN (logical one for CPLD, logical zero for module).
TE0703 CPLD can be select with JTAGEN (DIP-S2-3).
Module FPGA/CPLD access can be switched with PROGMODE which is driven by CMD0 (DIP-S2-2).CMD0 is pulled up with CPLD.
|OFF||OFF||1||1||Access to TE0703 CPLD|
|OFF||ON||1||0||Access to CPLD of B2B Module|
|ON||OFF||0||1||Access to TE0703 CPLD|
|ON||ON||0||0||Access to FPGA of B2B Module|
EN1 is set to one.
RESIN is driven by S1 (Push Button).
MODE Pin is sourced by MIO. MIO0 connected DIP S2-4 and B2B connector. MIO is pulled up with CPLD and can be set to GND via DIP.
|ON||0||def. SD-CARD Boot(for Zynq Modules)|
MIO14 is driven by BDBUS0 (FTDI RX).
BDBUS1 (FTDI TX) is driven by MIO14 .
MIO13 is driven by X16.
X17 is driven by MIO12.
|LED1 (D1-red)||ON, if CMD0=1 else not FTDI_RXD|
|LED2 (D2-green)||ON, if CMD0=1 else not FTDI_TXD|
Appx. A: Change History and Legal Notices
- REV01 to older REV01
- enable CPLD access to module CPLD over DIP
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
|Date||Document Revision||CPLD Firmware Revision||Supported PCB Revision||Authors||Description|
|Work in progress|
*some unused IOs are not connected
Appx. B: Legal Notices
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